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8. sed1565 series (rev. 1.2)
C i C sed1565 series sed1565 series contents general description ............................................................................................................ ....................... 8-1 features ....................................................................................................................... .................................... 8-1 block diagram .................................................................................................................. .............................. 8-3 pin dimensions ................................................................................................................. ............................... 8-4 pin descriptions ............................................................................................................... ........................... 8-20 description of functions ....................................................................................................... ................ 8-24 commands ....................................................................................................................... ............................... 8-48 command description ............................................................................................................ ................... 8-57 absolute maximum ratings ....................................................................................................... .............. 8-63 dc characteristics ............................................................................................................. ....................... 8-64 timing characteristics ......................................................................................................... ................... 8-72 the mpu interface (reference examples) ........................................................................................ 8 -80 connections between lcd drivers (reference example) .......................................................... 8-81 connections between lcd drivers (reference examples) ....................................................... 8-82 a sample tcp pin assignment .................................................................................................... .............. 8-83 external view of tcp pins ...................................................................................................... ................. 8-84 notice ......................................................................................................................... ..................................... 8-85
sed1565 series epson 8C1 sed1565 series general description the sed1565 series is a series of single-chip dot matrix liquid crystal display drivers that can be connected directly to a microprocessor bus. 8-bit parallel or serial display data sent from the microprocessor is stored in the internal display data ram and the chip generates a liquid crystal drive signal independent of the microprocessor. because the chips in the sed1565 series contain 65 132 bits of display data ram and there is a 1-to-1 correspondence between the liquid crystal panel pixels and the internal ram bits, these chips enable displays with a high degree of freedom. the sed1565 series chips contain 65 common output circuits and 132 segment output circuits, so that a single chip can drive a 65 132 dot display (capable of displaying 8 columns 4 rows of a 16 16 dot kanji font). the sed1567 series chips contain 33 common output circuits and 132 segment output circuits, so that a single chip can drive 33 132 dot display (capable of displaying 8 columns 2 rows of 16 16 dot kanji fonts). thanks to the built-in 55 common output circuits and 132 segment output circuits, the sed1568* ** is capable of displaying 55 132 dots (11 columns 4 lines using 11 12 dots kanji font) with a single chip. the sed1569 series chips contain 53 common output circuits and 132 segment output circuits, so that a single chip can drive 53 132 dot display (capable of displaying 11 columns 4 rows of 11 12 dot kanji fonts). moreover, the capacity of the display can be extended through the use of master/slave structures between chips. the chips are able to minimize power consumption because no external operating clock is necessary for the display data ram read/write operation. furthermore, because each chip is equipped internally with a low- power liquid crystal driver power supply, resistors for liquid crystal driver power voltage adjustment and a display clock cr oscillator circuit, the sed1565 series chips can be used to create the lowest power display system with the fewest components for high- performance portable devices. features ? direct display of ram data through the display data ram. ram bit data: 1 non-illuminated 0 illuminated (during normal display) ? ram capacity 65 132 = 8580 bits ? display driver circuits sed1565* ** : 65 common output and 132 segment outputs sed1566* ** : 49 common output and 132 segment outputs sed1567* ** : 33 common outputs and 132 segment outputs sed1568* ** : 55 common outputs and 132 segment outputs sed1569* ** : 53 common outputs and 132 segment outputs ? high-speed 8-bit mpu interface (the chip can be connected directly to the both the 80x86 series mpus and the 68000 series mpus) /serial interfaces are supported. ? abundant command functions display data read/write, display on/off, normal/ reverse display mode, page address set, display start line set, column address set, status read, display all points on/off, lcd bias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, common output status select, v5 voltage regulation internal resistor ratio set. ? static drive circuit equipped internally for indicators. (1 system, with variable flashing speed.) ? low-power liquid crystal display power supply circuit equipped internally. booster circuit (with boost ratios of double/triple/ quad, where the step-up voltage reference power supply can be input externally) high-accuracy voltage adjustment circuit (thermal gradient C0.05%/ c or C0.2%/ c or external input) v 5 voltage regulator resistors equipped internally, v 1 to v 4 voltage divider resistors equipped internally, electronic volume function equipped internally, voltage follower. ? cr oscillator circuit equipped internally (external clock can also be input) ? extremely low power consumption operating power when the built-in power supply is used (an example) sed1565d 0b 81 m a (v dd C v ss = v dd C v ss2 = /sed1565d bb 3.0 v, quad voltage, v 5 C v dd = C 11.0 v) sed1566d 0b 43 m a (v dd C v ss = v dd C v ss2 = /sed1566d bb 3.0 v, triple voltage, v 5 C v dd = C 8.0 v) sed1567d 0b 29 m a (v dd C v ss = v dd C v ss2 = /sed1567d bb 3.0 v, triple voltage, v 5 C v dd = C 8.0 v) sed1568d 0b /sed1568d bb /sed1569d 0b /sed1569d bb 46 m a (v dd C v ss = v dd C v ss2 = 3.0 v, triple voltage, v 5 C v dd = C 8.0 v) conditions: when all displays are in white and the normal mode is selected (see page 60 *12 for details of the conditions). ? power supply operable on the low 1.8 voltage logic power supply v dd C v ss = 1.8 v to C5.5 v boost reference voltage: v dd C v ss2 = 1.8 v to C6.0 v liquid crystal drive power supply: v dd C v 5 = C4.5 v to C16.0 v ? wide range of operating temperatures: C40 to 85 c ? cmos process ? shipping forms include bare chip and tcp. ? these chips not designed for resistance to light or resistance to radiation.
sed1565 series 8C2 epson series specifications product duty bias sed dr com dr v reg temperature shipping name gradient forms sed1565d 0b 1/65 1/9, 1/7 132 65 C0.05%/ c bare chip /sed1565d bb sed1565t 0 * 1/65 1/9, 1/7 132 65 C0.05%/ c tcp sed1565d 1b 1/65 1/9, 1/7 132 65 C0.2%/ c bare chip * sed1565t 1 * 1/65 1/9, 1/7 132 65 C0.2%/ c tcp sed1565d 2b 1/65 1/9, 1/7 132 65 external input bare chip * sed1565t 2 * 1/65 1/9, 1/7 132 65 external input tcp sed1566d 0b 1/49 1/8, 1/6 132 49 C0.05%/ c bare chip /sed1566d bb sed1566t 0 * 1/49 1/8, 1/6 132 49 C0.05%/ c tcp sed1566d 1b 1/49 1/8, 1/6 132 49 C0.2%/ c bare chip * sed1566t 1 * 1/49 1/8, 1/6 132 49 C0.2%/ c tcp sed1566d 2b 1/49 1/8, 1/6 132 49 external input bare chip * sed1566t 2 * 1/49 1/8, 1/6 132 49 external input tcp sed1567d 0b 1/33 1/6, 1/5 132 33 C0.05%/ c bare chip /sed1567d bb sed1567t 0 * 1/33 1/6, 1/5 132 33 C0.05%/ c tcp sed1567d 1b 1/33 1/6, 1/5 132 33 C0.2%/ c bare chip * sed1567t 1 * 1/33 1/6, 1/5 132 33 C0.2%/ c tcp sed1567d 2b 1/33 1/6, 1/5 132 33 external input bare chip * sed1567t 2 * 1/33 1/6, 1/5 132 33 external input tcp sed1568d 0b 1/55 1/8, 1/6 132 55 C0.05%/ c bare chip /sed1568d bb sed1569d 0b 1/53 1/8, 1/6 132 53 C0.05%/ c bare chip /sed1569d bb * sed1569t 0 * 1/53 1/8, 1/6 132 53 C0.05%/ c tcp * : under development
sed1565 series epson 8C3 sed1565 series v ss v dd v 1 v 2 v 3 v 4 v 5 v out v ss2 v r v rs irs hpm cap1+ cap1 cap2 cap2+ cap3+ frs cls oscillator circuit display timing generation circuit line address circuit i/o buffer page address circuit fr cl dof m/s cs1 cs2 a0 rd (e) wr (r/w) p/s res d7 (si) d6 (scl) d5 d4 d3 d2 d1 d0 seg0 seg131 com0 com63 coms ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? coms com drivers seg drivers display data latch circuit display data ram 132 x 65 column address circuit status command decoder mpu interface bus holder com output status select circuit power supply circuit block diagram example: sed1565* **
sed1565 series 8C4 epson chip size 10.82 mm 2.81 mm bump pitch 71 m m (min.) bump size pad no. 1~24 85 m m 85 m m pad no. 25~82 64 m m 85 m m pad no. 83~99 85 m m 85 m m pad no. 100 85 m m 73 m m pad no. 101~133 85 m m 47 m m pad no. 134 85 m m 73 m m pad no. 135 73 m m 85 m m pad no. 136~273 47 m m 85 m m pad no. 274 73 m m 85 m m pad no. 275 85 m m 73 m m pad no. 276~308 85 m m 47 m m pad no. 309 85 m m 73 m m bump height 17 m m (typ.) chip thickness 625 m m sed1565 series (0, 0) 100 99 1 135 274 134 309 275 die no. d1565d 0b pin dimensions
sed1565 series epson 8C5 sed1565 series sed1565* ** pad center coordinates pad pin xy no. name 1 (nc) 4973 1246 2 frs 4853 3 fr 4734 4 cl 4614 5 dof 4494 6 test0 4375 7v ss 4255 8 cs1 4136 9 cs2 4016 10 v dd 3896 11 res 3777 12 a0 3657 13 v ss 3538 14 wr, r/w 3418 15 rd, e 3298 16 v dd 3179 17 d0 3059 18 d1 2940 19 d2 2820 20 d3 2700 21 d4 2581 22 d5 2461 23 d6, scl 2342 24 d7, si 2222 25 (nc) 2119 26 v dd 2030 27 v dd 1941 28 v dd 1852 29 v dd 1763 30 v ss 1674 31 v ss 1585 32 v ss 1496 33 v ss2 1407 34 v ss2 1318 35 v ss2 1229 36 v ss2 1140 37 (nc) 1051 38 v out 962 39 v out 873 40 cap3C 784 pad pin xy no. name 41 cap3C 695 1246 42 (nc) 605 43 cap1+ 516 44 cap1+ 427 45 cap1C 338 46 cap1C 249 47 cap2C 160 48 cap2C 71 49 cap2+ C18 50 cap2+ C107 51 v ss C196 52 v ss C285 53 v rs C374 54 v rs C463 55 v dd C552 56 v dd C641 57 v 1 C730 58 v 1 C819 59 v 2 C908 60 v 2 C997 61 (nc) C1086 62 v 3 C1176 63 v 3 C1265 64 v 4 C1354 65 v 4 C1443 66 v 5 C1532 67 v 5 C1621 68 (nc) C1710 69 v r C1799 70 v r C1888 71 v dd C1977 72 v dd C2066 73 test1 C2155 74 test1 C2244 75 test2 C2333 76 test2 C2422 77 (nc) C2511 78 test3 C2600 79 test3 C2689 80 test4 C2778 pad pin xy no. name 81 test4 C2867 1246 82 (nc) C2957 83 v dd C3059 84 m/s C3179 85 cls C3298 86 v ss C3418 87 c86 C3538 88 p/s C3657 89 v dd C3777 90 hpm C3896 91 v ss C4016 92 irs C4136 93 v dd C4255 94 test5 C4375 95 test6 C4494 96 test7 C4614 97 test8 C4734 98 test9 C4853 99 (nc) C4973 100 (nc) C5252 1248 101 com31 1163 102 com30 1090 103 com29 1017 104 com28 945 105 com27 872 106 com26 799 107 com25 727 108 com24 654 109 com23 581 110 com22 509 111 com21 436 112 com20 363 113 com19 291 114 com18 218 115 com17 145 116 com16 73 117 com15 0 118 com14 C73 119 com13 C145 120 com12 C218 units: m m
sed1565 series 8C6 epson pad pin xy no. name 121 com11 C5252 C291 122 com10 C363 123 com9 C436 124 com8 C509 125 com7 C581 126 com6 C654 127 com5 C727 128 com4 C800 129 com3 C872 130 com2 C945 131 com1 C1018 132 com0 C1090 133 coms C1163 134 (nc) C1248 135 (nc) C5009 C1246 136 (nc) C4924 137 (nc) C4853 138 (nc) C4781 139 seg0 C4709 140 seg1 C4637 141 seg2 C4565 142 seg3 C4493 143 seg4 C4421 144 seg5 C4349 145 seg6 C4277 146 seg7 C4206 147 seg8 C4134 148 seg9 C4062 149 seg10 C3990 150 seg11 C3918 151 seg12 C3846 152 seg13 C3774 153 seg14 C3702 154 seg15 C3630 155 seg16 C3559 156 seg17 C3487 157 seg18 C3415 158 seg19 C3343 159 seg20 C3271 160 seg21 C3199 pad pin xy no. name 161 seg22 C3127 C1246 162 seg23 C3055 163 seg24 C2983 164 seg25 C2912 165 seg26 C2840 166 seg27 C2768 167 seg28 C2696 168 seg29 C2624 169 seg30 C2552 170 seg31 C2480 171 seg32 C2408 172 seg33 C2336 173 seg34 C2265 174 seg35 C2193 175 seg36 C2121 176 seg37 C2049 177 seg38 C1977 178 seg39 C1905 179 seg40 C1833 180 seg41 C1761 181 seg42 C1689 182 seg43 C1618 183 seg44 C1546 184 seg45 C1474 185 seg46 C1402 186 seg47 C1330 187 seg48 C1258 188 seg49 C1186 189 seg50 C1114 190 seg51 C1042 191 seg52 C971 192 seg53 C899 193 seg54 C827 194 seg55 C755 195 seg56 C683 196 seg57 C611 197 seg58 C539 198 seg59 C467 199 seg60 C395 200 seg61 C324 pad pin xy no. name 201 seg62 C252 C1246 202 seg63 C180 203 seg64 C108 204 seg65 C36 205 seg66 36 206 seg67 108 207 seg68 180 208 seg69 252 209 seg70 324 210 seg71 395 211 seg72 467 212 seg73 539 213 seg74 611 214 seg75 683 215 seg76 755 216 seg77 827 217 seg78 899 218 seg79 971 219 seg80 1042 220 seg81 1114 221 seg82 1186 222 seg83 1258 223 seg84 1330 224 seg85 1402 225 seg86 1474 226 seg87 1546 227 seg88 1618 228 seg89 1689 229 seg90 1761 230 seg91 1833 231 seg92 1905 232 seg93 1977 233 seg94 2049 234 seg95 2121 235 seg96 2193 236 seg97 2265 237 seg98 2336 238 seg99 2408 239 seg100 2480 240 seg101 2552 units: m m
sed1565 series epson 8C7 sed1565 series units: m m pad pin xy no. name 241 seg102 2624 C1246 242 seg103 2696 243 seg104 2768 244 seg105 2840 245 seg106 2912 246 seg107 2983 247 seg108 3055 248 seg109 3127 249 seg110 3199 250 seg111 3271 251 seg112 3343 252 seg113 3415 253 seg114 3487 254 seg115 3558 255 seg116 3630 256 seg117 3702 257 seg118 3774 258 seg119 3846 259 seg120 3918 260 seg121 3990 261 seg122 4062 262 seg123 4134 263 seg124 4206 264 seg125 4277 265 seg126 4349 266 seg127 4421 267 seg128 4493 268 seg129 4565 269 seg130 4637 270 seg131 4709 271 (nc) 4781 272 (nc) 4853 273 (nc) 4924 274 (nc) 5009 275 (nc) 5252 C1248 276 com32 C1163 277 com33 C1090 278 com34 C1018 279 com35 C945 280 com36 C872 pad pin xy no. name 281 com37 5252 C800 282 com38 C727 283 com39 C654 284 com40 C581 285 com41 C509 286 com42 C436 287 com43 C363 288 com44 C291 289 com45 C218 290 com46 C145 291 com47 C73 292 com48 0 293 com49 73 294 com50 145 295 com51 218 296 com52 291 297 com53 363 298 com54 436 299 com55 509 300 com56 581 301 com57 654 302 com58 727 303 com59 799 304 com60 872 305 com61 945 306 com62 1017 307 com63 1090 308 coms 1163 309 (nc) 1248
sed1565 series 8C8 epson sed1566* ** pad center coordinates pad pin xy no. name 1 (nc) 4973 1246 2 frs 4853 3 fr 4734 4 cl 4614 5 dof 4494 6 test0 4375 7v ss 4255 8 cs1 4136 9 cs2 4016 10 v dd 3896 11 res 3777 12 a0 3657 13 v ss 3538 14 wr, r/w 3418 15 rd, e 3298 16 v dd 3179 17 d0 3059 18 d1 2940 19 d2 2820 20 d3 2700 21 d4 2581 22 d5 2461 23 d6, scl 2342 24 d7, si 2222 25 (nc) 2119 26 v dd 2030 27 v dd 1941 28 v dd 1852 29 v dd 1763 30 v ss 1674 31 v ss 1585 32 v ss 1496 33 v ss2 1407 34 v ss2 1318 35 v ss2 1229 36 v ss2 1140 37 (nc) 1051 38 v out 962 39 v out 873 40 cap3C 784 pad pin xy no. name 41 cap3C 695 1246 42 (nc) 605 43 cap1+ 516 44 cap1+ 427 45 cap1C 338 46 cap1C 249 47 cap2C 160 48 cap2C 71 49 cap2+ C18 50 cap2+ C107 51 v ss C196 52 v ss C285 53 v rs C374 54 v rs C463 55 v dd C552 56 v dd C641 57 v 1 C730 58 v 1 C819 59 v 2 C908 60 v 2 C997 61 (nc) C1086 62 v 3 C1176 63 v 3 C1265 64 v 4 C1354 65 v 4 C1443 66 v 5 C1532 67 v 5 C1621 68 (nc) C1710 69 v r C1799 70 v r C1888 71 v dd C1977 72 v dd C2066 73 test1 C2155 74 test1 C2244 75 test2 C2333 76 test2 C2422 77 (nc) C2511 78 test3 C2600 79 test3 C2689 80 test4 C2778 pad pin xy no. name 81 test4 C2867 1246 82 (nc) C2957 83 v dd C3059 84 m/s C3179 85 cls C3298 86 v ss C3418 87 c86 C3538 88 p/s C3657 89 v dd C3777 90 hpm C3896 91 v ss C4016 92 irs C4136 93 v dd C4255 94 test5 C4375 95 test6 C4494 96 test7 C4614 97 test8 C4734 98 test9 C4853 99 (nc) C4973 100 (nc) C5252 1248 101 (nc) 1163 102 (nc) 1090 103 com23 1017 104 (nc) 945 105 com22 872 106 (nc) 799 107 com21 727 108 com20 654 109 com19 581 110 com18 509 111 com17 436 112 com16 363 113 com15 291 114 com14 218 115 com13 145 116 com12 73 117 com11 0 118 com10 C73 119 com9 C145 120 com8 C218 units: m m
sed1565 series epson 8C9 sed1565 series pad pin xy no. name 121 com7 C5252 C291 122 com6 C363 123 com5 C436 124 com4 C509 125 com3 C581 126 com2 C654 127 com1 C727 128 (nc) C800 129 com0 C872 130 (nc) C945 131 coms C1018 132 (nc) C1090 133 (nc) C1163 134 (nc) C1248 135 (nc) C5009 C1246 136 (nc) C4924 137 (nc) C4853 138 (nc) C4781 139 seg0 C4709 140 seg1 C4637 141 seg2 C4565 142 seg3 C4493 143 seg4 C4421 144 seg5 C4349 145 seg6 C4277 146 seg7 C4206 147 seg8 C4134 148 seg9 C4062 149 seg10 C3990 150 seg11 C3918 151 seg12 C3846 152 seg13 C3774 153 seg14 C3702 154 seg15 C3630 155 seg16 C3559 156 seg17 C3487 157 seg18 C3415 158 seg19 C3343 159 seg20 C3271 160 seg21 C3199 pad pin xy no. name 161 seg22 C3127 C1246 162 seg23 C3055 163 seg24 C2983 164 seg25 C2912 165 seg26 C2840 166 seg27 C2768 167 seg28 C2696 168 seg29 C2624 169 seg30 C2552 170 seg31 C2480 171 seg32 C2408 172 seg33 C2336 173 seg34 C2265 174 seg35 C2193 175 seg36 C2121 176 seg37 C2049 177 seg38 C1977 178 seg39 C1905 179 seg40 C1833 180 seg41 C1761 181 seg42 C1689 182 seg43 C1618 183 seg44 C1546 184 seg45 C1474 185 seg46 C1402 186 seg47 C1330 187 seg48 C1258 188 seg49 C1186 189 seg50 C1114 190 seg51 C1042 191 seg52 C971 192 seg53 C899 193 seg54 C827 194 seg55 C755 195 seg56 C683 196 seg57 C611 197 seg58 C539 198 seg59 C467 199 seg60 C395 200 seg61 C324 pad pin xy no. name 201 seg62 C252 C1246 202 seg63 C180 203 seg64 C108 204 seg65 C36 205 seg66 36 206 seg67 108 207 seg68 180 208 seg69 252 209 seg70 324 210 seg71 395 211 seg72 467 212 seg73 539 213 seg74 611 214 seg75 683 215 seg76 755 216 seg77 827 217 seg78 899 218 seg79 971 219 seg80 1042 220 seg81 1114 221 seg82 1186 222 seg83 1258 223 seg84 1330 224 seg85 1402 225 seg86 1474 226 seg87 1546 227 seg88 1618 228 seg89 1689 229 seg90 1761 230 seg91 1833 231 seg92 1905 232 seg93 1977 233 seg94 2049 234 seg95 2121 235 seg96 2193 236 seg97 2265 237 seg98 2336 238 seg99 2408 239 seg100 2480 240 seg101 2552 units: m m
sed1565 series 8C10 epson units: m m pad pin xy no. name 241 seg102 2624 C1246 242 seg103 2696 243 seg104 2768 244 seg105 2840 245 seg106 2912 246 seg107 2983 247 seg108 3055 248 seg109 3127 249 seg110 3199 250 seg111 3271 251 seg112 3343 252 seg113 3415 253 seg114 3487 254 seg115 3558 255 seg116 3630 256 seg117 3702 257 seg118 3774 258 seg119 3846 259 seg120 3918 260 seg121 3990 261 seg122 4062 262 seg123 4134 263 seg124 4206 264 seg125 4277 265 seg126 4349 266 seg127 4421 267 seg128 4493 268 seg129 4565 269 seg130 4637 270 seg131 4709 271 (nc) 4781 272 (nc) 4853 273 (nc) 4924 274 (nc) 5009 275 (nc) 5252 C1248 276 (nc) C1163 277 (nc) C1090 278 com24 C1018 279 (nc) C945 280 com25 C872 pad pin xy no. name 281 (nc) 5252 C800 282 com26 C727 283 com27 C654 284 com28 C581 285 com29 C509 286 com30 C436 287 com31 C363 288 com32 C291 289 com33 C218 290 com34 C145 291 com35 C73 292 com36 0 293 com37 73 294 com38 145 295 com39 218 296 com40 291 297 com41 363 298 com42 436 299 com43 509 300 com44 581 301 com45 654 302 com46 727 303 (nc) 799 304 com47 872 305 (nc) 945 306 coms 1017 307 (nc) 1090 308 (nc) 1163 309 (nc) 1248
sed1565 series epson 8C11 sed1565 series pad pin xy no. name 1 (nc) 4973 1246 2 frs 4853 3 fr 4734 4 cl 4614 5 dof 4494 6 test0 4375 7v ss 4255 8 cs1 4136 9 cs2 4016 10 v dd 3896 11 res 3777 12 a0 3657 13 v ss 3538 14 wr, r/w 3418 15 rd, e 3298 16 v dd 3179 17 d0 3059 18 d1 2940 19 d2 2820 20 d3 2700 21 d4 2581 22 d5 2461 23 d6, scl 2342 24 d7, si 2222 25 (nc) 2119 26 v dd 2030 27 v dd 1941 28 v dd 1852 29 v dd 1763 30 v ss 1674 31 v ss 1585 32 v ss 1496 33 v ss2 1407 34 v ss2 1318 35 v ss2 1229 36 v ss2 1140 37 (nc) 1051 38 v out 962 39 v out 873 40 cap3C 784 pad pin xy no. name 41 cap3C 695 1246 42 (nc) 605 43 cap1+ 516 44 cap1+ 427 45 cap1C 338 46 cap1C 249 47 cap2C 160 48 cap2C 71 49 cap2+ C18 50 cap2+ C107 51 v ss C196 52 v ss C285 53 v rs C374 54 v rs C463 55 v dd C552 56 v dd C641 57 v 1 C730 58 v 1 C819 59 v 2 C908 60 v 2 C997 61 (nc) C1086 62 v 3 C1176 63 v 3 C1265 64 v 4 C1354 65 v 4 C1443 66 v 5 C1532 67 v 5 C1621 68 (nc) C1710 69 v r C1799 70 v r C1888 71 v dd C1977 72 v dd C2066 73 test1 C2155 74 test1 C2244 75 test2 C2333 76 test2 C2422 77 (nc) C2511 78 test3 C2600 79 test3 C2689 80 test4 C2778 pad pin xy no. name 81 test4 C2867 1246 82 (nc) C2957 83 v dd C3059 84 m/s C3179 85 cls C3298 86 v ss C3418 87 c86 C3538 88 p/s C3657 89 v dd C3777 90 hpm C3896 91 v ss C4016 92 irs C4136 93 v dd C4255 94 test5 C4375 95 test6 C4494 96 test7 C4614 97 test8 C4734 98 test9 C4853 99 (nc) C4973 100 (nc) C5252 1248 101 com15 1163 102 com15 1090 103 com14 1017 104 com14 945 105 com13 872 106 com13 799 107 com12 727 108 com12 654 109 com11 581 110 com11 509 111 com10 436 112 com10 363 113 com9 291 114 com9 218 115 com8 145 116 com8 73 117 com7 0 118 com7 C73 119 com6 C145 120 com6 C218 sed1567* ** pad center coordinates units: m m
sed1565 series 8C12 epson pad pin xy no. name 121 com5 C5252 C291 122 com5 C363 123 com4 C436 124 com4 C509 125 com3 C581 126 com3 C654 127 com2 C727 128 com2 C800 129 com1 C872 130 com1 C945 131 com0 C1018 132 com0 C1090 133 coms C1163 134 (nc) C1248 135 (nc) C5009 C1246 136 (nc) C4924 137 (nc) C4853 138 (nc) C4781 139 seg0 C4709 140 seg1 C4637 141 seg2 C4565 142 seg3 C4493 143 seg4 C4421 144 seg5 C4349 145 seg6 C4277 146 seg7 C4206 147 seg8 C4134 148 seg9 C4062 149 seg10 C3990 150 seg11 C3918 151 seg12 C3846 152 seg13 C3774 153 seg14 C3702 154 seg15 C3630 155 seg16 C3559 156 seg17 C3487 157 seg18 C3415 158 seg19 C3343 159 seg20 C3271 160 seg21 C3199 pad pin xy no. name 161 seg22 C3127 C1246 162 seg23 C3055 163 seg24 C2983 164 seg25 C2912 165 seg26 C2840 166 seg27 C2768 167 seg28 C2696 168 seg29 C2624 169 seg30 C2552 170 seg31 C2480 171 seg32 C2408 172 seg33 C2336 173 seg34 C2265 174 seg35 C2193 175 seg36 C2121 176 seg37 C2049 177 seg38 C1977 178 seg39 C1905 179 seg40 C1833 180 seg41 C1761 181 seg42 C1689 182 seg43 C1618 183 seg44 C1546 184 seg45 C1474 185 seg46 C1402 186 seg47 C1330 187 seg48 C1258 188 seg49 C1186 189 seg50 C1114 190 seg51 C1042 191 seg52 C971 192 seg53 C899 193 seg54 C827 194 seg55 C755 195 seg56 C683 196 seg57 C611 197 seg58 C539 198 seg59 C467 199 seg60 C395 200 seg61 C324 pad pin xy no. name 201 seg62 C252 C1246 202 seg63 C180 203 seg64 C108 204 seg65 C36 205 seg66 36 206 seg67 108 207 seg68 180 208 seg69 252 209 seg70 324 210 seg71 395 211 seg72 467 212 seg73 539 213 seg74 611 214 seg75 683 215 seg76 755 216 seg77 827 217 seg78 899 218 seg79 971 219 seg80 1042 220 seg81 1114 221 seg82 1186 222 seg83 1258 223 seg84 1330 224 seg85 1402 225 seg86 1474 226 seg87 1546 227 seg88 1618 228 seg89 1689 229 seg90 1761 230 seg91 1833 231 seg92 1905 232 seg93 1977 233 seg94 2049 234 seg95 2121 235 seg96 2193 236 seg97 2265 237 seg98 2336 238 seg99 2408 239 seg100 2480 240 seg101 2552 units: m m
sed1565 series epson 8C13 sed1565 series pad pin xy no. name 241 seg102 2624 C1246 242 seg103 2696 243 seg104 2768 244 seg105 2840 245 seg106 2912 246 seg107 2983 247 seg108 3055 248 seg109 3127 249 seg110 3199 250 seg111 3271 251 seg112 3343 252 seg113 3415 253 seg114 3487 254 seg115 3558 255 seg116 3630 256 seg117 3702 257 seg118 3774 258 seg119 3846 259 seg120 3918 260 seg121 3990 261 seg122 4062 262 seg123 4134 263 seg124 4206 264 seg125 4277 265 seg126 4349 266 seg127 4421 267 seg128 4493 268 seg129 4565 269 seg130 4637 270 seg131 4709 271 (nc) 4781 272 (nc) 4853 273 (nc) 4924 274 (nc) 5009 275 (nc) 5252 C1248 276 com16 C1163 277 com16 C1090 278 com17 C1018 279 com17 C945 280 com18 C872 pad pin xy no. name 281 com18 5252 C800 282 com19 C727 283 com19 C654 284 com20 C581 285 com20 C509 286 com21 C436 287 com21 C363 288 com22 C291 289 com22 C218 290 com23 C145 291 com23 C73 292 com24 0 293 com24 73 294 com25 145 295 com25 218 296 com26 291 297 com26 363 298 com27 436 299 com27 509 300 com28 581 301 com28 654 302 com29 727 303 com29 799 304 com30 872 305 com30 945 306 com31 1017 307 com31 1090 308 coms 1163 309 (nc) 1248 units: m m
sed1565 series 8C14 epson sed1568* ** pad center coordinates units: m m pad pin xy no. name 1 (nc) 4973 1246 2 frs 4853 3 fr 4734 4 cl 4614 5 dof 4494 6 test0 4375 7v ss 4255 8 cs1 4136 9 cs2 4016 10 v dd 3896 11 res 3777 12 a0 3657 13 v ss 3538 14 wr, r/w 3418 15 rd, e 3298 16 v dd 3179 17 d0 3059 18 d1 2940 19 d2 2820 20 d3 2700 21 d4 2581 22 d5 2461 23 d6, scl 2342 24 d7, si 2222 25 (nc) 2119 26 v dd 2030 27 v dd 1941 28 v dd 1852 29 v dd 1763 30 v ss 1674 31 v ss 1585 32 v ss 1496 33 v ss2 1407 34 v ss2 1318 35 v ss2 1229 36 v ss2 1140 37 (nc) 1051 38 v out 962 39 v out 873 40 cap3C 784 pad pin xy no. name 41 cap3C 695 1246 42 (nc) 605 43 cap1+ 516 44 cap1+ 427 45 cap1C 338 46 cap1C 249 47 cap2C 160 48 cap2C 71 49 cap2+ C18 50 cap2+ C107 51 v ss C196 52 v ss C285 53 v rs C374 54 v rs C463 55 v dd C552 56 v dd C641 57 v 1 C730 58 v 1 C819 59 v 2 C908 60 v 2 C997 61 (nc) C1086 62 v 3 C1176 63 v 3 C1265 64 v 4 C1354 65 v 4 C1443 66 v 5 C1532 67 v 5 C1621 68 (nc) C1710 69 v r C1799 70 v r C1888 71 v dd C1977 72 v dd C2066 73 test1 C2155 74 test1 C2244 75 test2 C2333 76 test2 C2422 77 (nc) C2511 78 test3 C2600 79 test3 C2689 80 test4 C2778 pad pin xy no. name 81 test4 C2867 1246 82 (nc) C2957 83 v dd C3059 84 m/s C3179 85 cls C3298 86 v ss C3418 87 c86 C3538 88 p/s C3657 89 v dd C3777 90 hpm C3896 91 v ss C4016 92 irs C4136 93 v dd C4255 94 test5 C4375 95 test6 C4494 96 test7 C4614 97 test8 C4734 98 test9 C4853 99 (nc) C4973 100 (nc) C5252 1248 101 (nc) 1163 102 com26 1090 103 (nc) 1017 104 com25 945 105 com25 872 106 com23 799 107 com22 727 108 com21 654 109 com20 581 110 com19 509 111 com18 436 112 com17 363 113 com16 291 114 com15 218 115 com14 145 116 com13 73 117 com12 0 118 com11 C73 119 com10 C145 120 com9 C218
sed1565 series epson 8C15 sed1565 series pad pin xy no. name 121 com8 C5252 C291 122 com7 C363 123 com6 C436 124 com5 C509 125 com4 C581 126 com3 C654 127 com2 C727 128 com1 C800 129 (nc) C872 130 com0 C945 131 (nc) C1018 132 coms C1090 133 (nc) C1163 134 (nc) C1248 135 (nc) C5009 C1246 136 (nc) C4924 137 (nc) C4853 138 (nc) C4781 139 seg0 C4709 140 seg1 C4637 141 seg2 C4565 142 seg3 C4493 143 seg4 C4421 144 seg5 C4349 145 seg6 C4277 146 seg7 C4206 147 seg8 C4134 148 seg9 C4062 149 seg10 C3990 150 seg11 C3918 151 seg12 C3846 152 seg13 C3774 153 seg14 C3702 154 seg15 C3630 155 seg16 C3559 156 seg17 C3487 157 seg18 C3415 158 seg19 C3343 159 seg20 C3271 160 seg21 C3199 pad pin xy no. name 161 seg22 C3127 C1246 162 seg23 C3055 163 seg24 C2983 164 seg25 C2912 165 seg26 C2840 166 seg27 C2768 167 seg28 C2696 168 seg29 C2624 169 seg30 C2552 170 seg31 C2480 171 seg32 C2408 172 seg33 C2336 173 seg34 C2265 174 seg35 C2193 175 seg36 C2121 176 seg37 C2049 177 seg38 C1977 178 seg39 C1905 179 seg40 C1833 180 seg41 C1761 181 seg42 C1689 182 seg43 C1618 183 seg44 C1546 184 seg45 C1474 185 seg46 C1402 186 seg47 C1330 187 seg48 C1258 188 seg49 C1186 189 seg50 C1114 190 seg51 C1042 191 seg52 C971 192 seg53 C899 193 seg54 C827 194 seg55 C755 195 seg56 C683 196 seg57 C611 197 seg58 C539 198 seg59 C467 199 seg60 C395 200 seg61 C324 pad pin xy no. name 201 seg62 C252 C1246 202 seg63 C180 203 seg64 C108 204 seg65 C36 205 seg66 36 206 seg67 108 207 seg68 180 208 seg69 252 209 seg70 324 210 seg71 395 211 seg72 467 212 seg73 539 213 seg74 611 214 seg75 683 215 seg76 755 216 seg77 827 217 seg78 899 218 seg79 971 219 seg80 1042 220 seg81 1114 221 seg82 1186 222 seg83 1258 223 seg84 1330 224 seg85 1402 225 seg86 1474 226 seg87 1546 227 seg88 1618 228 seg89 1689 229 seg90 1761 230 seg91 1833 231 seg92 1905 232 seg93 1977 233 seg94 2049 234 seg95 2121 235 seg96 2193 236 seg97 2265 237 seg98 2336 238 seg99 2408 239 seg100 2480 240 seg101 2552 units: m m
sed1565 series 8C16 epson pad pin xy no. name 241 seg102 2624 C1246 242 seg103 2696 243 seg104 2768 244 seg105 2840 245 seg106 2912 246 seg107 2983 247 seg108 3055 248 seg109 3127 249 seg110 3199 250 seg111 3271 251 seg112 3343 252 seg113 3415 253 seg114 3487 254 seg115 3558 255 seg116 3630 256 seg117 3702 257 seg118 3774 258 seg119 3846 259 seg120 3918 260 seg121 3990 261 seg122 4062 262 seg123 4134 263 seg124 4206 264 seg125 4277 265 seg126 4349 266 seg127 4421 267 seg128 4493 268 seg129 4565 269 seg130 4637 270 seg131 4709 271 (nc) 4781 272 (nc) 4853 273 (nc) 4924 274 (nc) 5009 275 (nc) 5252 C1248 276 (nc) C1163 277 com27 C1090 278 (nc) C1018 279 com28 C945 280 (nc) C872 pad pin xy no. name 281 com29 5252 C800 282 com30 C727 283 com31 C654 284 com32 C581 285 com33 C509 286 com34 C436 287 com35 C363 288 com36 C291 289 com37 C218 290 com38 C145 291 com39 C73 292 com40 0 293 com41 73 294 com42 145 295 com43 218 296 com44 291 297 com45 363 298 com46 436 299 com47 509 300 com48 581 301 com48 654 302 com50 727 303 com51 799 304 com52 872 305 com53 945 306 (nc) 1017 307 coms 1090 308 (nc) 1163 309 (nc) 1248 units: m m
sed1565 series epson 8C17 sed1565 series pad pin xy no. name 1 (nc) 4973 1246 2 frs 4853 3 fr 4734 4 cl 4614 5 dof 4494 6 test0 4375 7v ss 4255 8 cs1 4136 9 cs2 4016 10 v dd 3896 11 res 3777 12 a0 3657 13 v ss 3538 14 wr, r/w 3418 15 rd, e 3298 16 v dd 3179 17 d0 3059 18 d1 2940 19 d2 2820 20 d3 2700 21 d4 2581 22 d5 2461 23 d6, scl 2342 24 d7, si 2222 25 (nc) 2119 26 v dd 2030 27 v dd 1941 28 v dd 1852 29 v dd 1763 30 v ss 1674 31 v ss 1585 32 v ss 1496 33 v ss2 1407 34 v ss2 1318 35 v ss2 1229 36 v ss2 1140 37 (nc) 1051 38 v out 962 39 v out 873 40 cap3C 784 pad pin xy no. name 41 cap3C 695 1246 42 (nc) 605 43 cap1+ 516 44 cap1+ 427 45 cap1C 338 46 cap1C 249 47 cap2C 160 48 cap2C 71 49 cap2+ C18 50 cap2+ C107 51 v ss C196 52 v ss C285 53 v rs C374 54 v rs C463 55 v dd C552 56 v dd C641 57 v 1 C730 58 v 1 C819 59 v 2 C908 60 v 2 C997 61 (nc) C1086 62 v 3 C1176 63 v 3 C1265 64 v 4 C1354 65 v 4 C1443 66 v 5 C1532 67 v 5 C1621 68 (nc) C1710 69 v r C1799 70 v r C1888 71 v dd C1977 72 v dd C2066 73 test1 C2155 74 test1 C2244 75 test2 C2333 76 test2 C2422 77 (nc) C2511 78 test3 C2600 79 test3 C2689 80 test4 C2778 pad pin xy no. name 81 test4 C2867 1246 82 (nc) C2957 83 v dd C3059 84 m/s C3179 85 cls C3298 86 v ss C3418 87 c86 C3538 88 p/s C3657 89 v dd C3777 90 hpm C3896 91 v ss C4016 92 irs C4136 93 v dd C4255 94 test5 C4375 95 test6 C4494 96 test7 C4614 97 test8 C4734 98 test9 C4853 99 (nc) C4973 100 (nc) C5252 1248 101 (nc) 1163 102 com25 1090 103 (nc) 1017 104 com24 945 105 (nc) 872 106 com23 799 107 com22 727 108 com21 654 109 com20 581 110 com19 509 111 com18 436 112 com17 363 113 com16 291 114 com15 218 115 com14 145 116 com13 73 117 com12 0 118 com11 C73 119 com10 C145 120 com9 C218 sed1569* ** pad center coordinates units: m m
sed1565 series 8C18 epson pad pin xy no. name 121 com8 C5252 C291 122 com7 C363 123 com6 C436 124 com5 C509 125 com4 C581 126 com3 C654 127 com2 C727 128 com1 C800 129 (nc) C872 130 com0 C945 131 (nc) C1018 132 coms C1090 133 (nc) C1163 134 (nc) C1248 135 (nc) C5009 C1246 136 (nc) C4924 137 (nc) C4853 138 (nc) C4781 139 seg0 C4709 140 seg1 C4637 141 seg2 C4565 142 seg3 C4493 143 seg4 C4421 144 seg5 C4349 145 seg6 C4277 146 seg7 C4206 147 seg8 C4134 148 seg9 C4062 149 seg10 C3990 150 seg11 C3918 151 seg12 C3846 152 seg13 C3774 153 seg14 C3702 154 seg15 C3630 155 seg16 C3559 156 seg17 C3487 157 seg18 C3415 158 seg19 C3343 159 seg20 C3271 160 seg21 C3199 pad pin xy no. name 161 seg22 C3127 C1246 162 seg23 C3055 163 seg24 C2983 164 seg25 C2912 165 seg26 C2840 166 seg27 C2768 167 seg28 C2696 168 seg29 C2624 169 seg30 C2552 170 seg31 C2480 171 seg32 C2408 172 seg33 C2336 173 seg34 C2265 174 seg35 C2193 175 seg36 C2121 176 seg37 C2049 177 seg38 C1977 178 seg39 C1905 179 seg40 C1833 180 seg41 C1761 181 seg42 C1689 182 seg43 C1618 183 seg44 C1546 184 seg45 C1474 185 seg46 C1402 186 seg47 C1330 187 seg48 C1258 188 seg49 C1186 189 seg50 C1114 190 seg51 C1042 191 seg52 C971 192 seg53 C899 193 seg54 C827 194 seg55 C755 195 seg56 C683 196 seg57 C611 197 seg58 C539 198 seg59 C467 199 seg60 C395 200 seg61 C324 pad pin xy no. name 201 seg62 C252 C1246 202 seg63 C180 203 seg64 C108 204 seg65 C36 205 seg66 36 206 seg67 108 207 seg68 180 208 seg69 252 209 seg70 324 210 seg71 395 211 seg72 467 212 seg73 539 213 seg74 611 214 seg75 683 215 seg76 755 216 seg77 827 217 seg78 899 218 seg79 971 219 seg80 1042 220 seg81 1114 221 seg82 1186 222 seg83 1258 223 seg84 1330 224 seg85 1402 225 seg86 1474 226 seg87 1546 227 seg88 1618 228 seg89 1689 229 seg90 1761 230 seg91 1833 231 seg92 1905 232 seg93 1977 233 seg94 2049 234 seg95 2121 235 seg96 2193 236 seg97 2265 237 seg98 2336 238 seg99 2408 239 seg100 2480 240 seg101 2552 units: m m
sed1565 series epson 8C19 sed1565 series pad pin xy no. name 241 seg102 2624 C1246 242 seg103 2696 243 seg104 2768 244 seg105 2840 245 seg106 2912 246 seg107 2983 247 seg108 3055 248 seg109 3127 249 seg110 3199 250 seg111 3271 251 seg112 3343 252 seg113 3415 253 seg114 3487 254 seg115 3558 255 seg116 3630 256 seg117 3702 257 seg118 3774 258 seg119 3846 259 seg120 3918 260 seg121 3990 261 seg122 4062 262 seg123 4134 263 seg124 4206 264 seg125 4277 265 seg126 4349 266 seg127 4421 267 seg128 4493 268 seg129 4565 269 seg130 4637 270 seg131 4709 271 (nc) 4781 272 (nc) 4853 273 (nc) 4924 274 (nc) 5009 275 (nc) 5252 C1248 276 (nc) C1163 277 com26 C1090 278 (nc) C1018 279 com27 C945 280 (nc) C872 pad pin xy no. name 281 com28 5252 C800 282 com29 C727 283 com30 C654 284 com31 C581 285 com32 C509 286 com33 C436 287 com34 C363 288 com35 C291 289 com36 C218 290 com37 C145 291 com38 C73 292 com39 0 293 com40 73 294 com41 145 295 com42 218 296 com43 291 297 com44 363 298 com45 436 299 com46 509 300 com47 581 301 com48 654 302 com49 727 303 com50 799 304 (nc) 872 305 com51 945 306 (nc) 1017 307 coms 1090 308 (nc) 1163 309 (nc) 1248 units: m m
sed1565 series 8C20 epson pin descriptions power supply pins pin name i/o function no. of pins v dd power shared with the mpu power supply terminal v cc .13 supply v ss power this is a 0v terminal connected to the system gnd. 9 supply v ss2 power this is the reference power supply for the step-up voltage circuit for the 4 supply liquid crystal drive. v rs power this is the externally-input vreg power supply for the lcd power supply 2 supply voltage regulator. these are only enabled for the models with the vreg external input option. v 1 , v 2 , power this is a multi-level power supply for the liquid crystal drive. the voltage 10 v 3 , v 4 , supply applied is determined by the liquid crystal cell, and is changed through the v 5 use of a resistive voltage divided or through changing the impedance using an op. amp. voltage levels are determined based on vdd, and must maintain the relative magnitudes shown below. v dd (= v 0 ) 3 v 1 3 v 2 3 v 3 3 v 4 3 v 5 master operation: when the power supply turns on, the internal power supply circuits produce the v1 to v4 voltages shown below. the voltage settings are selected using the lcd bias set command. lcd power supply circuit terminals pin name i/o function no. of pins cap1+ o dc/dc voltage converter. connect a capacitor between this terminal and 2 the cap1- terminal. cap1C o dc/dc voltage converter. connect a capacitor between this terminal and 2 the cap1+ terminal. cap2+ o dc/dc voltage converter. connect a capacitor between this terminal and 2 the cap2- terminal. cap2C o dc/dc voltage converter. connect a capacitor between this terminal and 2 the cap2+ terminal. cap3C o dc/dc voltage converter. connect a capacitor between this terminal and 2 the cap1+ terminal. v out o dc/dc voltage converter. connect a capacitor between this terminal and 2 v ss . v r i output voltage regulator terminal. provides the voltage between v dd and 2 v5 through a resistive voltage divider. these are only enabled when the v 5 voltage regulator internal resistors are not used (irs = l). these cannot be used when the v 5 voltage regulator internal resistors are used (irs = h). sed1565* ** sed1566* ** sed1567* ** sed1568* ** sed1569* ** v 1 1/9?v 5 1/7?v 5 1/8?v 5 1/6?v 5 1/6?v 5 1/5?v 5 1/8?v 5 1/6?v 5 1/8?v 5 1/6?v 5 v 2 2/9?v 5 2/7?v 5 2/8?v 5 2/6?v 5 2/6?v 5 2/5?v 5 2/8?v 5 2/6?v 5 2/8?v 5 2/6?v 5 v 3 7/9?v 5 5/7?v 5 6/8?v 5 4/6?v 5 4/6?v 5 3/5?v 5 6/8?v 5 4/6?v 5 6/8?v 5 4/6?v 5 v 4 8/9?v 5 6/7?v 5 7/8?v 5 5/6?v 5 5/6?v 5 4/5?v 5 7/8?v 5 5/6?v 5 7/6?v 5 5/6?v 5
sed1565 series epson 8C21 sed1565 series system bus connection terminals pin name i/o function no. of pins d7 to d0 i/o this is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit 8 standard mpu data bus. (si) when the serial interface is selected (p/s = l), then d7 serves as the (scl) serial data input terminal (si) and d6 serves as the serial clock input terminal (scl). at this time, d0 to d5 are set to high impedance. when the chip select is inactive, d0 to d7 are set to high impedance. a0 i this is connect to the least significant bit of the normal mpu address bus, 1 and it determines whether the data bits are data or a command. a0 = h: indicates that d0 to d7 are display data. a0 = l: indicates that d0 to d7 are control data. res i when res is set to l, the settings are initialized. 1 the reset operation is performed by the res signal level. cs1 i this is the chip select signal. when cs1 = l and cs2 = h, then the 2 cs2 chip select becomes active, and data/command i/o is enabled. rd i ? when connected to an 8080 mpu, this is active low. 1 (e) this pin is connected to the rd signal of the 8080 mpu, and the sed1565 series data bus is in an output status when this signal is l. ? when connected to a 6800 series mpu, this is active high. this is the 68000 series mpu enable clock input terminal. wr i ? when connected to an 8080 mpu, this is active low. 1 (r/w) this terminal connects to the 8080 mpu wr signal. the signals on the data bus are latched at the rising edge of the wr signal. ? when connected to a 6800 series mpu: this is the read/write control signal input terminal. when r/w = h: read. when r/w = l: write. c86 i this is the mpu interface switch terminal. 1 c86 = h: 6800 series mpu interface. c86 = l: 8080 mpu interface. p/s i this is the parallel data input/serial data input switch terminal. 1 p/s = h: parallel data input. p/s = l: serial data input. the following applies depending on the p/s status: when p/s = l, d0 to d5 are hz. d0 to d5 may be h, l or open. rd (e) and wr (p/w) are fixed to either h or l. with serial data input, ram display data reading is not supported. p/s data/command data read/write serial clock h a0 d0 to d7 rd, wr l a0 si (d7) write only scl (d6)
sed1565 series 8C22 epson pin name i/o function no. of pins cls i terminal to select whether or enable or disable the display clock internal 1 oscillator circuit. cls = h: internal oscillator circuit is enabled cls = l: internal oscillator circuit is disabled (requires external input) when cls = l, input the display clock through the cl terminal. m/s i this terminal selects the master/slave operation for the sed1565 series 1 chips. master operation outputs the timing signals that are required for the lcd display, while slave operation inputs the timing signals required for the liquid crystal display, synchronizing the liquid crystal display system. m/s = h: master operation m/s = l: slave operation the following is true depending on the m/s and cls status: cl i/o this is the display clock input terminal 1 the following is true depending on the m/s and cls status. when the sed1565 series chips are used in master/slave mode, the various cl terminals must be connected. fr i/o this is the liquid crystal alternating current signal i/o terminal. 1 m/s = h: output m/s = l: input when the sed1565 series chip is used in master/slave mode, the various fr terminals must be connected. dof i/o this is the liquid crystal display blanking control terminal. 1 m/s = h: output m/s = l: input when the sed1565 series chip is used in master/slave mode, the various dof terminals must be connected. frs o this is the output terminal for the static drive. 1 this terminal is only enabled when the static indicator display is on when in master operation mode, and is used in conjunction with the fr terminal. irs i this terminal selects the resistors for the v5 voltage level adjustment. 1 irs = h: use the internal resistors irs = l: do not use the internal resistors. the v5 voltage level is regulated by an external resistive voltage divider attached to the vr terminal. this pin is enabled only when the master operation mode is selected. it is fixed to either h or l when the slave operation mode is selected. hpm i this is the power control terminal for the power supply circuit for liquid 1 crystal drive. hpm = h: normal mode hpm = l: high power mode this pin is enabled only when the master operation mode is selected. it is fixed to either h or l when the slave operation mode is selected. oscillator power m/s cls circuit supply cl fr frs dof circuit h h enabled enabled output output output output l disabled enabled input output output output l h disabled disabled input input output input l disabled disabled input input output input m/s cls cl h h output l input l h input l input
sed1565 series epson 8C23 sed1565 series pin name i/o function no. of pins seg0 o these are the liquid crystal segment drive outputs. through a combination 132 to of the contents of the display ram and with the fr signal, a single level is seg131 selected from v dd , v 2 , v 3 , and v 5 . com0 o these are the liquid crystal common drive outputs. to comn through a combination of the contents of the scan data and with the fr signal, a single level is selected from v dd , v 1 , v 4 , and v 5 . coms o these are the com output terminals for the indicator. both terminals 2 output the same signal. leave these open if they are not used. when in master/slave mode, the same signal is output by both master and slave. liquid crystal drive terminals ram data fr output voltage normal display reverse display hh v dd v 2 hl v 5 v 3 lh v 2 v dd ll v 3 v 5 power save v dd scan data fr output voltage hh v 5 hl v dd lh v 1 ll v 4 power save v dd test terminals pin name i/o function no. of pins test0 to 4 i/o these are terminals for ic chip testing. 12 test7 to 9 they are set to open. test5, 6 i these are terminals for ic chip testing. 2 they are set to v dd . total: 288 pins for the sed1565 * ** . 272 pins for the sed1566 * ** . 256 pins for the sed1567 * ** . part no. com sed1565* ** com 0 ~ com 63 sed1566* ** com 0 ~ com 47 sed1567* ** com 0 ~ com 31 sed1568* ** com 0 ~ com 53 sed1569* ** com 0 ~ com 51 part no. sed1565* ** 64 sed1566* ** 48 sed1567* ** 32 sed1568* ** 54 sed1569* ** 52
sed1565 series 8C24 epson description of functions the mpu interface selecting the interface type with the sed1565 series chips, data transfers are done through an 8-bit bi-directional data bus (d7 to d0) or through a serial data input (si). through selecting the p/ s terminal polarity to the h or l it is possible to select either parallel data input or serial data input as shown in table 1. the parallel interface when the parallel interface has been selected (p/s = h), then it is possible to connect directly to either an 8080-system mpu or a 6800 series mpu (as shown in table 2) by selecting the c86 terminal to either h or to l. moreover, data bus signals are recognized by a combination of a0, rd (e), wr (r/w) signals, as shown in table 3. table 3 shared 6800 series 8080 series function a0 r/w rd wr 1 1 0 1 reads the display data 1 0 1 0 writes the display data 0 1 0 1 status read 0 0 1 0 write control data (command) table 2 p/s cs1 cs2 a0 rd wr d7~d0 h: 6800 series mpu bus cs1 cs2 a0 e r/w d7~d0 l: 8080 mpu bus cs1 cs2 a0 rd wr d7~d0 table 1 p/s cs1 cs2 a0 rd wr c86 d7 d6 d5~d0 h: parallel input cs1 cs2 a0 rd wr c86 d7 d6 d5~d0 l: serial input cs1 cs2 a0 si scl (hz) indicates fixed to either h or to l
sed1565 series epson 8C25 sed1565 series the serial interface when the serial interface has been selected (p/s = l) then when the chip is in active state (cs1 = l and cs2 = h) the serial data input (si) and the serial clock input (scl) can be received. the serial data is read from the serial data input pin in the rising edge of the serial clocks d7, d6 through d0, in this order. this data is converted to 8 bits parallel data in the rising edge of the eighth serial clock for the processing. the a0 input is used to determine whether or the serial data input is display data or command data; when a0 = h, the data is display data, and when a0 = l then the data is command data. the a0 input is read and used for detection every 8th rising edge of the serial clock after the chip becomes active. figure 1 is a serial interface signal chart. figure 1 * when the chip is not active, the shift registers and the counter are reset to their initial states. * reading is not possible while in serial interface mode. * caution is required on the scl signal when it comes to line-end reflections and external noise. we recommend that operation be rechecked on the actual equipment. the chip select the sed1565 series chips have two chip select terminals: cs1 and cs2. the mpu interface or the serial interface is enabled only when cs1 = l and cs2 = h. when the chip select is inactive, d0 to d7 enter a high impedance state, and the a0, rd, and wr inputs are inactive. when the serial interface is selected, the shift register and the counter are reset. accessing the display data ram and the internal registers data transfer at a higher speed is ensured since the mpu is required to satisfy the cycle time ( t cyc ) requirement alone in accessing the sed1565 series. wait time may not be considered. and, in the sed1565 series chips, each time data is sent from the mpu, a type of pipeline process between lsis is performed through the bus holder attached to the internal data bus. for example, when the mpu writes data to the display data ram, once the data is stored in the bus holder, then it is written to the display data ram before the next data write cycle. moreover, when the mpu reads the display data ram, the first data read cycle (dummy) stores the read data in the bus holder, and then the data is read from the bus holder to the system bus at the next data read cycle. there is a certain restriction in the read sequence of the display data ram. please be advised that data of the specified address is not generated by the read instruction issued immediately after the address setup. this data is generated in data read of the second time. thus, a dummy read is required whenever the address setup or write cycle operation is conducted. this relationship is shown in figure 2. cs1 cs2 si scl a0 d7 1234567891011121314 d6 d5 d4 d3 d2 d7 d6 d5 d4 d3 d2 d1 d0
sed1565 series 8C26 epson the busy flag when the busy flag is 1 it indicates that the sed1565 series chip is running internal processes, and at this time no command aside from a status read will be received. the busy flag is outputted to d7 pin with the n n n+1 n+2 n+3 n+1 n+2 n+3 wr mpu internal timing data latch bus holder write signal n n n n+1 n+2 increment n+1 preset n n n n+1 n+2 data read #n+1 data read #n dummy read address set #n internal timing wr rd data address preset read signal column address bus holder mpu writing reading read instruction. if the cycle time ( t cyc ) is maintained, it is not necessary to check for this flag before each command. this makes vast improvements in mpu processing capabilities possible. figure 2
sed1565 series epson 8C27 sed1565 series d0 d1 d2 d3 d4 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 display data ram com0 com1 com2 com3 com4 liquid crystal display display data ram display data ram the display data ram is a ram that stores the dot data for the display. it has a 65 (8 page x 8 bit +1) x 132 bit structure. it is possible to access the desired bit by specifying the page address and the column address. because, as is shown in figure 3, the d7 to d0 display data from the mpu corresponds to the liquid crystal display common direction, there are few constraints at the time of display data transfer when multiple sed1565 series chips are used, thus and display structures can be created easily and with a high degree of freedom. moreover, reading from and writing to the display ram from the mpu side is performed through the i/o buffer, which is an independent operation from signal reading for the liquid crystal driver. consequently, even if the display data ram is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering). table 4 seg seg0 seg 131 output adc 0 0 (h) ? column address ? 83 (h) (d0) 1 83 (h) ? column address ? 0 (h) figure 3 the page address circuit as shown in figure 6-4, page address of the display data ram is specified through the page address set command. the page address must be specified again when changing pages to perform access. page address 8 (d3, d2, d1, d0 = 1, 0, 0, 0) is the page for the ram region used only by the indicators, and only display data d0 is used. the column addresses as is shown in figure 4, the display data ram column address is specified by the column address set command. the specified column address is incremented (+1) with each display data read/write command. this allows the mpu display data to be accessed continuously. moreover, the incrementation of column addresses stops with 83h. because the column address is independent of the page address, when moving, for example, from page 0 column 83h to page 1 column 00h, it is necessary to respecify both the page address and the column address. furthermore, as is shown in table 4, the adc command (segment driver direction select command) can be used to reverse the relationship between the display data ram column address and the segment output. because of this, the constraints on the ic layout when the lcd module is assembled can be minimized. the line address circuit the line address circuit, as shown in table 4, specifies the line address relating to the com output when the contents of the display data ram are displayed. using the display start line address set command, what is normally the top line of the display can be specified (this is the com0 output when the common output mode is normal, and the com63 output for sed1565 series, com47 output for sed1566 series and com31 output for the sed1567 series when the common output mode is reversed. the display area is a 65 line area for the sed1565 series, a 49 line are for the sed1566 and a 33 line area for the sed1567 series from the display start line address. if the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed.
sed1565 series 8C28 epson d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 11h 12h 13h 14h 15h 16h 17h 18h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh 2ch 2dh 2eh 2fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 3bh 3ch 3dh 3eh 3fh com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 coms 0 0 0 0 page 0 0 0 0 1 page 1 0 0 1 0 page 2 0 0 1 1 page 3 0 1 0 0 page 4 0 1 0 1 page 5 0 1 1 0 page 6 0 1 1 1 page 7 1000 page 8 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 83 82 81 80 7f 7e 7d 7c 00 01 02 03 04 05 06 07 seg127 seg125 seg126 seg127 seg128 seg129 seg130 seg131 07 06 05 04 03 02 01 00 7c 7d 7e 7f 80 81 82 83 lcd out adc column address 1 d0 0 d0 regardless of the display start line address, the sed1565 series accesses 65th line, the sed1566 series accesses 49th line and the sed1567 series accesses 33th line and the sed1568 series accesses 55th line, the sed1569 series accesses 53 lines. start 63 lines 52 lines 48 lines page address d3 d2 d1 d0 data line address com output when the common output mode is normal 32 lines 54 lines figure 4
sed1565 series epson 8C29 sed1565 series the display data latch circuit the display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data ram. because the display normal/reverse status, display on/ off status, and display all points on/off commands control only the data within the latch, they do not change the data within the display data ram itself. the oscillator circuit this is a cr-type oscillator that produces the display clock. the oscillator circuit is only enabled when m/s = h and cls = h. when cls = l the oscillation stops, and the display clock is input through the cl terminal. display timing generator circuit the display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. the display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. reading to the display data liquid crystal driver circuits is completely independent of accesses to the display data ram by the mpu. consequently, even if the display data ram is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (fr) from the display clock. it generates a drive wave form using a 2 frame alternating current drive method, as is shown in figure 5, for the liquid crystal drive circuit. figure 5 64 cl fr com0 v dd v dd v dd v 1 v 1 v 4 v 5 v 4 v 2 v 3 v 5 v 5 com1 ram data segn 65 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6 two-frame alternating current drive wave form (sed1565* ** )
sed1565 series 8C30 epson when multiple sed1565 series chips are used, the slave chips must be supplied the display timing signals (fr, cl, dof) from the master chip[s]. table 5 shows the status of the fr, cl, and dof signals. table 5 operating mode fr cl dof master (m/s = h) the internal oscillator circuit is enabled (cls = h) output output output the internal oscillator circuit is disabled (cls = l) output input output slave (m/s = l) the internal oscillator circuit is enabled (cls = h) input input input the internal oscillator circuit is disabled (cls = l) input input input the common output status select circuit in the sed1565 series chips, the com output scan direction can be selected by the common output status select command. (see table 6.) consequently, the constraints in ic layout at the time of lcd module assembly can be minimized. the liquid crystal driver circuits these are a 197-channel (sed1565 series), a 181- channel (sed1566 series) multiplexers 165-channel (sed1567 series) and a 185-channel (sed1569 series) that generate four voltage levels for driving the liquid crystal. the combination of the display data, the com scan signal, and the fr signal produces the liquid crystal drive voltage output. figure 6 shows examples of the seg and com output wave form. table 6 status com scan direction sed1565* ** sed1566* ** sed1567* ** sed1568* ** sed1569* ** normal com0 ? com63 com0 ? com47 com0 ? com31 com0 ? com53 com0 ? com51 reverse com63 ? com0 com47 ? com0 com31 ? com0 com53 ? com0 com51 ? com0
sed1565 series epson 8C31 sed1565 series figure 6 com0 com1 com2 com3 com4 com5 com6 com7 fr com0 com1 com2 seg0 seg1 seg2 com0?eg0 com0?eg1 com8 com9 com10 com11 com12 com13 com14 com15 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 5 v 4 v 3 ? 3 ? 4 ? 5 v 2 v 1 v ? 1 ? 2 v 5 v 4 v 3 ? 3 ? 4 ? 5 v 2 v 1 v ? 1 ? 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v ss
sed1565 series 8C32 epson the power supply circuits the power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the liquid crystal drivers. they comprise booster circuits, voltage regulator circuits, and voltage follower circuits. they are only enabled in master operation. the power supply circuits can turn the booster circuits, the voltage regulator circuits, and the voltage follower circuits on of off independently through the use of the power control set command. consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. table 7 shows the power control set command 3-bit data control function, and table 8 shows reference combinations. table 7 the control details of each bit of the power control set command item status 1 0 d2 booster circuit control bit on off d1 voltage regulator circuit (v regulator circuit) control bit on off d0 voltage follower circuit (v/f circuit) control bit on off table 8 reference combinations v external step-up use settings d2 d1 d0 step-up regulator v/f voltage voltage circuit circuit circuit input system terminal 1 only the internal power supply is 1 1 1 o o o v ss2 used used 2 only the v regulator circuit and 0 1 1 x o o v out , v ss2 open the v/f circuit are used 3 only the v/f circuit is used 0 0 1 x x o v 5 , v ss2 open 4 only the external power supply is 0 0 0 x x x v 1 to v 5 open used * the step-up system terminals refer cap1+, cap1C, cap2+, cap2C, and cap3C. * while other combinations, not shown above, are also possible, these combinations are not recommended because they have no practical use. the step-up voltage circuits using the step-up voltage circuits equipped within the sed1565 series chips it is possible to product a quad step-up, a triple step-up, and a double step-up of the v dd C v ss2 voltage levels. quad step-up: connect capacitor c1 between cap1+ and cap1C, between cap2+ and cap2C, between cap1+ and cap3C, and between v ss2 and v out , to produce a voltage level in the negative direction at the v out terminal that is 4 times the voltage level between v dd and v ss2 . triple step-up: connect capacitor c1 between cap1+ and cap1C, between cap2+ and cap2C and between v ss2 and v out , and short between cap3C and v out to produce a voltage level in the negative direction at the v out terminal that is 3 times the voltage difference between v dd and v ss2 . double step-up: connect capacitor c1 between cap1+ and cap1C, and between v ss2 and v out , leave cap2+ open, and short between cap2C, cap3C and v out to produce a voltage in the negative direction at the v out terminal that is twice the voltage between v dd and v ss2 . the step-up voltage relationships are shown in figure 7.
sed1565 series epson 8C33 sed1565 series v ss2 v out cap3 cap1+ cap1 cap2 cap2+ c1 c1 c1 c1 + + + sed1565 series 4 x step-up voltage circuit 3 x step-up voltage circuit 2 x step-up voltage circuit v ss2 v out cap3 cap1+ cap1 cap2 cap2+ c1 c1 c1 + + + sed1565 series v ss2 v out cap3 cap1+ cap1 cap2 cap2+ open c1 c1 + + sed1565 series v dd = 0v v ss2 = ?v v out = 4 x v ss2 = ?2v 4x step-up voltage relationships v dd = 0v v ss2 = ?v v out = 3 x v ss2 = ?v 3x step-up voltage relationships v dd = 0v v ss2 = ?v v out = 2 x v ss2 = ?0v 2x step-up voltage relationships (a) when the v 5 voltage regulator internal resistors are used through the use of the v 5 voltage regulator internal resistors and the electronic volume function the liquid crystal power supply voltage v 5 can be controlled by commands alone (without adding any external resistors), making it possible to adjust the liquid crystal display brightness. the v 5 voltage can be calculated using equation a-1 over the range where | v 5 | < | v out |. the voltage regulator circuit the step-up voltage generated at v out outputs the liquid crystal driver voltage v 5 through the voltage regulator circuit. because the sed1565 series chips have an internal high-accuracy fixed voltage power supply with a 64- level electronic volume function and internal resistors for the v 5 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components. moreover, in the sed1565 series, three types of thermal gradients have been prepared as v reg options: (1) approximately -0.05%/ c (2) approximately -0.2%/ c, and (3) external input (supplied to the v rs terminal). figure 7 * the v ss2 voltage range must be set so that the v out terminal voltage does not exceed the absolute maximum rated value.
sed1565 series 8C34 epson figure 8 rb/ra is the v 5 voltage regulator internal resistor ratio, and can be set to 8 different levels through the v 5 voltage regulator internal resistor ratio set command. the (1 + rb/ra) ratio assumes the values shown in table 11 depending on the 3-bit data settings in the v 5 voltage regulator internal resistor ratio register. a is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic volume register. table 10 shows the value for a depending on the electronic volume register settings. table 9 equipment type thermal gradient units v reg units (1) internal power supply C0.05 [%/ c ] C2.1 [v] (2) internal power supply C0.2 [%/ c ] C4.9 [v] (3) external input v rs [v] table 10 d5 d4 d3 d2 d1 d0 a 000000 63 000001 62 000010 61 .. .. .. 111101 2 111110 1 111111 0 v ev (constant voltage supply + electronic volume) internal ra + internal rb v dd v 5 (equation a-1) v reg is the ic-internal fixed voltage supply, and its voltage at ta = 25 c is as shown in table 9. v rb ra v rb ra v vv ev reg ev reg 5 1 11 162 1 162 =+ ? ? ? =+ ? ? ? ? ? ? =- () [] a a q \
sed1565 series epson 8C35 sed1565 series table 11 sed1565* ** sed1566* ** register equipment type by thermal gradient [units: %/ c ] equipment type by thermal gradient [units: %/ c ] d2 d1 d0 (1) C0.05 (2) C0.2 (3) v reg external input (1) C0.05 (2) C0.2 (3) v reg external input 0 0 0 3.0 1.3 1.5 3.0 1.3 1.5 0 0 1 3.5 1.5 2.0 3.5 1.5 2.0 0 1 0 4.0 1.8 2.5 4.0 1.8 2.5 0 1 1 4.5 2.0 3.0 4.5 2.0 3.0 1 0 0 5.0 2.3 3.5 5.0 2.3 3.5 1 0 1 5.5 2.5 4.0 5.4 2.5 4.0 1 1 0 6.0 2.8 4.5 5.9 2.8 4.5 1 1 1 6.4 3.0 5.0 6.4 3.0 5.0 v 5 voltage regulator internal resistance ratio register value and (1 + rb/ra) ratio (reference value) figs. 9, 10, 11 (for sed1565 series), 12, 13, 14 (for sed1566 series) and figs. 15, 16, 17 show v 5 voltage measured by values of the internal resistance ratio resistor for v 5 voltage adjustment and electric volume resister for each temperature grade model, when ta = 25 c. sed1567* ** sed1568* ** /sed1569* ** register equipment type by thermal gradient [units: %/ c ] equipment type by thermal gradient [units: %/ c ] d2 d1 d0 (1) C0.05 (2) C0.2 (3) v reg external input C0.05 0 0 0 3.0 1.3 1.5 3 0 0 1 3.5 1.5 2.0 3.5 0 1 0 4.0 1.8 2.5 4 0 1 1 4.5 2.0 3.0 4.5 1 0 0 5.0 2.3 3.5 5 1 0 1 5.4 2.5 4.0 5.4 1 1 0 5.9 2.8 4.5 5.9 1 1 1 6.4 3.0 5.0 6.4
sed1565 series 8C36 epson sed1565d 0b /sed1565d bb figure 9: sed1565d 0b /sed1565d bb (1) for models where the thermal gradient = -0.05%/ c the v 5 voltage as a function of the v 5 voltage regulator internal resistor ratio register and the electronic volume register. sed1565d 1b figure 10: sed1565d 1b (2) for models where the thermal gradient = -0.2%/ c the v 5 voltage as a function of the v 5 voltage regulator internal resistor ratio register and the electronic volume register. ?6 ?5 ?4 ?3 ?2 ?1 ?0 ? ? ? ? ? ? ? ? ? 0 v5 [v] 00h 18h 30h 3fh electric volume resister 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 the v 5 voltage regulator internal resistance ratio registers (d2, d1, d0) ?6 ?5 ?4 ?3 ?2 ?1 ?0 ? ? ? ? ? ? ? ? ? 0 v5 [v] 00h 18h 30h 3fh electric volume resister the v 5 voltage regulator internal resistance ratio registers (d2, d1, d0) 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0
sed1565 series epson 8C37 sed1565 series sed1565d 2b figure 11: sed1565d 2b (3) for models with external input the v 5 voltage as a function of the v 5 voltage regulator internal resistor ratio register and the electronic volume register. sed1566d 0b /sed1566d bb figure 12: sed1566d 0b /sed1566d bb (1) for models where the thermal gradient = -0.05%/ c the v 5 voltage as a function of the v 5 voltage regulator internal resistor ratio register and the electronic volume register. ?6 ?5 ?4 ?3 ?2 ?1 ?0 ? ? ? ? ? ? ? ? ? 0 v5 [v] 00h 18h 30h 3fh electric volume resister the v 5 voltage regulator internal resistance ratio registers (d2, d1, d0) 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 ?6 ?5 ?4 ?3 ?2 ?1 ?0 ? ? ? ? ? ? ? ? ? 0 v5 [v] 00h 18h 30h 3fh electric volume resister the v 5 voltage regulator internal resistance ratio registers (d2, d1, d0) 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0
sed1565 series 8C38 epson sed1566d 1b figure 13: sed1566d 1b (2) for models where the thermal gradient = -0.2%/ c the v 5 voltage as a function of the v 5 voltage regulator internal resistor ratio register and the electronic volume register. sed1566d 2b figure 14: sed1566d 2b (3) for models with external input the v 5 voltage as a function of the v 5 voltage regulator internal resistor ratio register and the electronic volume register. ?6 ?5 ?4 ?3 ?2 ?1 ?0 ? ? ? ? ? ? ? ? ? 0 v5 [v] 00h 18h 30h 3fh electric volume resister the v 5 voltage regulator internal resistance ratio registers (d2, d1, d0) 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 ?6 ?5 ?4 ?3 ?2 ?1 ?0 ? ? ? ? ? ? ? ? ? 0 v5 [v] 00h 18h 30h 3fh electric volume resister the v 5 voltage regulator internal resistance ratio registers (d2, d1, d0) 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0
sed1565 series epson 8C39 sed1565 series sed1567d 0b /sed1567d bb figure 15: sed1567d 0b /sed1567d bb (1) for models where the thermal gradient = -0.05%/ c the v 5 voltage as a function of the v 5 voltage regulator internal resistor ratio register and the electronic volume register. sed1567d 1b figure 16: sed1567d 1b (2) for models where the thermal gradient = -0.2%/ c the v 5 voltage as a function of the v 5 voltage regulator internal resistor ratio register and the electronic volume register. ?6 ?5 ?4 ?3 ?2 ?1 ?0 ? ? ? ? ? ? ? ? ? 0 v5 [v] 00h 18h 30h 3fh electric volume resister the v 5 voltage regulator internal resistance ratio registers (d2, d1, d0) 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 ?6 ?5 ?4 ?3 ?2 ?1 ?0 ? ? ? ? ? ? ? ? ? 0 v5 [v] 00h 18h 30h 3fh electric volume resister the v 5 voltage regulator internal resistance ratio registers (d2, d1, d0) 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0
sed1565 series 8C40 epson sed1567d 2b figure 17: sed1567d 2b (3) for models with external input the v 5 voltage as a function of the v 5 voltage regulator internal resistor ratio register and the electronic volume register. sed1568d 0b /sed1568d bb figure 18: sed1568d 0b /sed1568d bb (1) for models where the thermal gradient = C0.05%/ c the v 5 voltage as a function of the v 5 voltage regulator internal resistor ratio register and the electronic volume register. ?6 ?5 ?4 ?3 ?2 ?1 ?0 ? ? ? ? ? ? ? ? ? 0 v5 [v] 00h 18h 30h 3fh electric volume resister the v 5 voltage regulator internal resistance ratio registers (d2, d1, d0) 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 ?6 ?5 ?4 ?3 ?2 ?1 ?0 ? ? ? ? ? ? ? ? ? 0 v5 [v] 00h 18h 30h 3fh electric volume resister 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 the v 5 voltage regulator internal resistance ratio registers (d2, d1, d0)
sed1565 series epson 8C41 sed1565 series sed1569d 0b /sed1569d bb figure 19: sed1569d 0b /sed1569d bb (temperature gradient = C0.05%/ c model the v 5 voltage as a function of the v 5 voltage regulator internal resistor ratio register and the electronic volume register. ?6 ?5 ?4 ?3 ?2 ?1 ?0 ? ? ? ? ? ? ? ? ? 0 v5 [v] 00h 18h 30h 3fh electric volume resister the v 5 voltage regulator internal resistance ratio registers (d2, d1, d0) 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 setup example: when selecting ta = 25 c and v 5 = 7 v for an sed1567 model on which temperature gradient = C0.05%/ c. using figure 15 and the equation a-1, the following setup is enabled. at this time, the variable range and the notch width of the v 5 voltage is, as shown table 13, as dependent on the electronic volume. table 12 contents register d5 d4 d3 d2 d1 d0 for v 5 voltage 0 1 0 regulator electronic volume 1 0 0101 table 13 v 5 min typ max units variable range C8.4 (63 levels) C6.8 (central value) C5.1 (0 level) [v] notch width 51 [mv]
sed1565 series 8C42 epson v rb ra v rb ra v vv ev reg ev reg 5 1 11 162 1 162 =+ ? ? ? =+ ? ? ? ? ? ? =- () [] ? ? ? ? a a q ( equation b-1) figure 20 \ v ev (fixed voltage power supply + electronic volume) external resistor ra' + external resistor rb' v dd v 5 (b) when an external resistance is used (i.e., the v5 voltage regulator internal resistors are not used) (1) the liquid crystal power supply voltage v 5 can also be set without using the v5 voltage regulator internal resistors (irs terminal = l) by adding resistors ra and rb between v dd and v r , and between v r and v 5 , respectively. when this is done, the use of the electronic volume function makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal power supply voltage v 5 through commands. in the range where | v 5 | < | v out |, the v 5 voltage can be calculated using equation b-1 based on the external resistances ra and rb. setup example: when selecting ta = 25 c and v 5 = C 7 v for an sed1567 series model where the temperature gradient = C0.05%/ c. when the central value of the electron volume register is (d5, d4, d3, d2, d1, d0) = (1, 0, 0, 0, 0, 0), then a = 31 and v reg = C2.1 v so, according to equation b-1, v rb ra v v rb ra reg 5 11 162 11 1 1 31 162 21 =+ ? ? ? - ? ? ? -=+ ? ? ? - ? ? ? - () ? ? ? ? . a (equation b-2) moreover, when the value of the current running through ra and rb is set to 5 m a, ra rb m ??. += 14 w (equation b-3) consequently, by equations b-2 and b-3, rb ra ra k rb k ? ? . ? ? = =w =w 312 340 1060 at this time, the v 5 voltage variable range and notch width, based on the electron volume function, is as given in table 14. table 14 v 5 min typ max units variable range C8.6 (63 levels) C7.0 (central value) C5.3 (0 level) [v] notch width 52 [mv]
sed1565 series epson 8C43 sed1565 series v rr r rr v rr r rr v vv ev reg ev reg 5 32 2 12 32 2 12 1 11 162 1 162 =+ +- +d ? ? ? ? =+ +-d +d ? ? ? ? ? ? ? =- () [] d a a q (equation c-1) figure 21 \ v ev (fixed voltage supply + electronic volume) external resistor r 1 d r 2 external resistor r 2 v r external resistor r 3 + v dd v 5 rb' ra' (c) when external resistors are used (i.e. the v 5 voltage regulator internal resistors are not used). (2) when the external resistor described above are used, adding a variable resistor as well makes it possible to perform fine adjustments on ra and rb, to set the liquid crystal drive voltage v 5 . in this case, the use of the electronic volume function makes it possible to control the liquid crystal power supply voltage v 5 by commands to adjust the liquid crystal display brightness. in the range where | v 5 | < | v out | the v 5 voltage can be calculated by equation c-1 below based on the r 1 and r 2 (variable resistor) and r 3 settings, where r 2 can be subjected to fine adjustments ( d r 2 ). setup example: when selecting ta = 25 c and v 5 = C 5 to C9 v (using r2) for an sed1567 model where the temperature gradient = C0.05%/ c. when the central value for the electronic volume register is set at (d5, d4, d3, d2, d1, d0) = (1, 0, 0, 0, 0, 0), a = =- 31 21 vv reg . so, according to equation c-1, when d r 2 = 0 w , in order to make v 5 = C9 v, -=+ + ? ? ? ? - ? ? ? - () 91 1 31 162 21 32 1 v rr r . (equation c-2) when d r 2 = r 2 , in order to make v = C5 v, -=+ + ? ? ? ? - ? ? ? - () 51 1 31 162 21 3 12 v r rr . (equation c-3) moreover, when the current flowing v dd and v 5 is set to 5 m a, rr r m 123 14 ++= w . (equation c-4) with this, according to equation c-2, c-3 and c-4, rk rk rk 1 2 3 264 211 925 =w =w =w at this time, the v 5 voltage variable range and notch width based on the electron volume function is as shown in table 15. table 15 v 5 min typ max units variable range C8.7 (63 levels) C7.0 (central value) C5.3 (0 level) [v] notch width 53 [mv]
sed1565 series 8C44 epson sequence step1 step2 end details (command, status) display off display all points on internal power supply off command address d7 1 1 d6 0 0 d5 1 1 d4 0 0 power saver commands (compound) d3 1 0 d2 1 1 d1 1 0 d0 0 1 high power mode the power supply circuit equipped in the sed1565 series chips has very low power consumption (normal mode: hpm = h). however, for lcds or panels with large loads, this low-power power supply may cause display quality to degrade. when this occurs, setting the hpm terminal to l (high power mode) can improve the quality of the display. we recommend that the display be checked on actual equipment to determine whether or not to use this mode. moreover, if the improvement to the display is inadequate even after high power mode has been set, then it is necessary to add a liquid crystal drive power supply externally. the internal power supply shutdown command sequence the sequence shown in figure 22 is recommended for shutting down the internal power supply, first placing the power supply in power saver mode and then turning the power supply off. * when the v 5 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands. moreover, it is necessary to provide a voltage from v out when the booster circuit is off. * the v r terminal is enabled only when the v 5 voltage regulator internal resistors are not used (i.e. the irs terminal = l). when the v 5 voltage regulator internal resistors are used (i.e. when the irs terminal = h), then the v r terminal is left open. * because the input impedance of the v r terminal is high, it is necessary to take into consideration short leads, shield cables, etc. to handle noise. the liquid crystal voltage generator circuit the v 5 voltage is produced by a resistive voltage divider within the ic, and can be produced at the v 1 , v 2 , v 3 , and v 4 voltage levels required for liquid crystal driving. moreover, when the voltage follower changes the impedance, it provides v 1 , v 2 , v 3 and v 4 to the liquid crystal drive circuit. 1/9 bias or 1/7 bias for sed1565 series, 1/8 bias or 1/6 bias for sed1566 series and 1/6 bias or 1/5 bias for the sed1567 series can be selected. figure 22
sed1565 series epson 8C45 sed1565 series v dd v dd v dd v ss c 1 v ss2 v out cap3 cap1+ cap1 cap2+ cap2 v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s c 1 c 1 c 1 c 2 c 2 c 2 c 2 c 2 sed1565 series v dd v ss c 1 v ss2 v out cap3 cap1+ cap1 cap2+ cap2 v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s c 1 c 1 c 1 r 3 r 2 r 1 c 2 c 2 c 2 c 2 c 2 sed1565 series (1) when the voltage regulator internal resistor is used. (example where v ss2 = v ss , with 4x step-up) (2) when the voltage regulator internal resistor is not used. (example where v ss2 = v ss , with 4x step-up) when used all of the step-up circuit, voltage regulating circuit and v/f circuit v dd v dd v ss external power supply v ss2 v out cap3 cap1+ cap1 cap2+ cap2 v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s c 2 c 2 c 2 c 2 c 2 sed1565 series v dd v dd v ss v ss2 v out cap3 cap1+ cap1 cap2+ cap2 v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s r 3 r 2 r 1 c 2 c 2 c 2 c 2 c 2 sed1565 series when the voltage regulator circuit and v/f circuit alone are used (1) when the v 5 voltage regulator internal resistor is not used. (2) when the v 5 voltage regulator internal resistor is used. external power supply reference circuit examples figure 22 shows reference circuit examples.
sed1565 series 8C46 epson figure 23 * 1 because the v r terminal input impedance is high, use short leads and shielded lines. * 2 c1 and c2 are determined by the size of the lcd being driven. select a value that will stabilize the liquid crystal drive voltage. example of the process by which to determine the settings: ? turn the voltage regulator circuit and voltage follower circuit on and supply a voltage to v out from the outside. ? determine c2 by displaying an lcd pattern with a heavy load (such as horizontal stripes) and selecting a c2 that stabilizes the liquid crystal drive voltages (v 1 to v 5 ). note that all c2 capacitors must have the same capacitance value. ? next turn all the power supplies on and determine c1. v dd v dd external power supply v ss v ss2 v out cap3 cap1+ cap1 cap2+ cap2 v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s sed1565 series ? when the built-in power is not used v dd v dd v ss external power supply v ss2 v out cap3 cap1+ cap1 cap2+ cap2 v 5 v r v dd v 1 v 2 v 3 v 4 v 5 irs m/s c 2 c 2 c 2 c 2 c 2 sed1565 series a when the v/f circuit alone is used examples of shared reference settings when v 5 can vary between C8 and 12 v item set value units c 1 1.0 to 4.7 m f c 2 0.01 to 1.0 m f v dd , v 0 v 1 v 2 v 3 v 4 v 5 r 4 r 4 r 4 r 4 c 2 sed1565 series reference set value r 4 : 100k w ~ 1m w it is recommended to set an optimum resistance value r 4 taking the liquid crystal display and the drive waveform. 5 when the built-in power circuit is used to drive a liquid crystal panel heavily loaded with ac or dc, it is recommended to connect an external resistor to stabilize potentials of v 1 , v 2 , v 3 and v 4 which are output from the built-in voltage follower.
sed1565 series epson 8C47 sed1565 series the reset circuit when the res input comes to the l level, these lsis return to the default state. their default states are as follows: 1. display off 2. normal display 3. adc select: normal (adc command d0 = l) 4. power control register: (d2, d1, d0) = (0, 0, 0) 5. serial interface internal register data clear 6. lcd power supply bias rate: sed1565* ** ............................................... 1/9 bias sed1566* ** , 1568* ** , 1569* ** ....... 1/8 bias sed1567* ** ............................................... 1/6 bias 7. all-indicator lamps-on off (all-indicator lamps on/off command d0 = l) 8. power saving clear 9. v 5 voltage regulator internal resistors ra and rb separation (in case of sed1565d bb , sed1566d bb , sed1567d bb , sed1568d bb and sed1569d bb , internal resistors are connected while res is l.) 10. output conditions of seg and com terminals seg : v 2 /v 3 , com : v 1 /v 4 (in case of sed1565d bb , sed1566d bb , sed1567d bb , sed1568d bb and sed1569d bb , both the seg terminal and the com terminal output the vda level while res is l. in case of other models, the seg terminal outputs v 2 and the com terminal outputs v 1 while res is l.) 11. read modify write off 12. static indicator off static indicator register : (d1, d2) = (0, 0) 13. display start line set to first line 14. column address set to address 0 15. page address set to page 0 16. common output status normal 17. v 5 voltage regulator internal resistor ratio set mode clear 18. electronic volume register set mode clear electronic volume register : (d5, d4, d3, d2, d1, d0) = (1, 0. 0, 0, 0, 0) 19. test mode clear on the other hand, when the reset command is used, the above default settings from 11 to 19 are only executed. when the power is turned on, the ic internal state becomes unstable, and it is necessary to initialize it using the res terminal. after the initialization, each input terminal should be controlled normally. moreover, when the control signal from the mpu is in the high impedance, an overcurrent may flow to the ic. after applying a current, it is necessary to take proper measures to prevent the input terminal from getting into the high impedance state. if the internal liquid crystal power supply circuit is not used on sed1565d bb , sed1566d bb , sed1567d bb , sed1568d bb and sed1569d bb , it is necessary that res is h when the external liquid crystal power supply is turned on. this ic has the function to discharge v 5 when res is l, and the external power supply short-circuits to v dd when res is l. while res is l, the oscillator and the display timing generator stop, and the cl, fr, frs and dof terminals are fixed to h. the terminals d0 to d7 are not affected. the v dd level is output from the seg and com output terminals. this means that an internal resistor is connected between v dd and v 5 . when the internal liquid crystal power supply circuit is not used on other models of sed1565 series, it is necessary that re is l when the external liquid crystal power supply is turned on. while res is l, the oscillator works but the display timing generator stops, and the cl, fr, frs and dof terminals are fixed to h. the terminals d0 to d7 are not affected.
sed1565 series 8C48 epson commands the sed1565 series chips identify the data bus signals by a combination of a0, rd (e), wr (r/w) signals. command interpretation and execution does not depend on the external clock, but rather is performed through internal timing only, and thus the processing is fast enough that normally a busy check is not required. in the 8080 mpu interface, commands are launched by inputting a low pulse to the rd terminal for reading, and inputting a low pulse to the wr terminal for writing. in the 6800 series mpu interface, the interface is placed in a read mode when an h signal is input to the r/w terminal and placed in a write mode when a l signal is input to the r/ w terminal and then the command is launched by inputting a high pulse to the e terminal. (see 10. timing characteristics regarding the timing.) consequently, the 6800 series mpu interface is different than the 80x86 series mpu interface in that in the explanation of commands and the display commands the status read and display data read rd (e) becomes 1(h). in the explanations below the commands are explained using the 8080 series mpu interface as the example. when the serial interface is selected, the data is input in sequence starting with d7. display on/off this command turns the display on and off. when the display off command is executed when in the display all points on mode, power saver mode is entered. see the section on the power saver for details. display start line set this command is used to specify the display start line address of the display data ram shown in figure 4. for further details see the explanation of this function in the line address circuit. page address set this command specifies the page address corresponding to the low address when the mpu accesses the display data ram (see figure 4). specifying the page address and column address enables to access a desired bit of the display data ram. changing the page address does not accompany a change in the status display. see the page address circuit in the function description (page 1C20) for the detail. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 line address 0 1 0 01000000 0 000001 1 000010 2 111110 62 111111 63 e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 page address 0 1 0 10110000 0 0001 1 0010 2 0111 7 1000 8 e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 0 1 0 10101111 display on 0 display off
sed1565 series epson 8C49 sed1565 series column address set this command specifies the column address of the display data ram shown in figure 4. the column address is split into two sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). each time the display data ram is accessed, the column address automatically increments (+1), making it possible for the mpu to continuously read from/write to the display data. the column address increment is topped at 83h. this does not change the page address continuously. see the function explanation in the column address circuit, for details. status read display data write this command writes 8-bit data to the specified display data ram address. since the column address is automatically incremented by 1 after the write, the mpu can write the display data. display data read this command reads 8-bit data from the specified display data ram address. since the column address is automatically incremented by 1 after the read, the cpu can continuously read multiple-word data. one dummy read is required immediately after the column address has been set. see the function explanation in display data ram for the explanation of accessing the internal registers. when the serial interface is used, reading of the display data becomes unavailable. busy when busy = 1, it indicates that either processing is occurring internally or a reset condition is in process. while the chip does not accept commands until busy = 0, if the cycle time can be satisfied, there is no need to check for busy conditions. adc this shows the relationship between the column address and the segment driver. 0: reverse (column address 131-n ? seg n) 1: normal (column address n ? seg n) (the adc command switches the polarity.) on/off on/off: indicates the display on/off state. 0: display on 1: display off (this display on/off command switches the polarity.) reset this indicates that the chip is in the process of initialization either because of a res signal or because of a reset command. 0: operating state 1: reset in progress e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 write data e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 read data e r/w column a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 a7 a6 a5 a4 a3 a2 a1 a0 address 0 1 0 0001a7a6a5a400000000 0 0a3a2a1a000000001 1 00000010 2 10000010 130 10000011 131 high bits ? low bits ? e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 busy adc on/off reset 0 0 0 0
sed1565 series 8C50 epson adc select (segment driver direction select) this command can reverse the correspondence between the display ram data column address and the segment driver output. thus, sequence of the segment driver output pins may be reversed by the command. see the column address circuit (page 1C20) for the detail. increment of the column address (by 1) accompanying the reading or writing the display data is done according to the column address indicated in figure 4. display normal/reverse this command can reverse the lit and unlit display without overwriting the contents of the display data ram. when this is done the display data ram contents are maintained. display all points on/off this command makes it possible to force all display points on regardless of the content of the display data ram. the contents of the display data ram are maintained when this is done. this command takes priority over the display normal/reverse command. when the display is in an off mode, executing the display all points on command will place the display in power save mode. for details, see the (20) power save section. lcd bias set this command selects the voltage bias ratio required for the liquid crystal display. read/modify/write this command is used paired with the end command. once this command has been input, the display data read command does not change the column address, but only the display data write command increments (+1) the column address. this mode is maintained until the end command is input. when the end command is input, the column address returns to the address it was at when the read/modify/write command was entered. this function makes it possible to reduce the load on the mpu when there are repeating data changes in a specified display region, such as when there is a blanking cursor. * even in read/modify/write mode, other commands aside from display data read/write commands can also be used. however, the column address set command cannot be used. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 0 1 0 1 0 1 0 0 0 0 0 normal 1 reverse e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 0 1 0 1 0 1 0 0 1 1 0 ram data h lcd on voltage (normal) 1 ram data l lcd on voltage (reverse) e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 setting 0 1 0 1 0 1 0 0 1 0 0 normal display mode 1 display all points on e r/w select status a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 sed1565* ** sed1566* ** sed1567* ** sed1568* ** sed1569* ** 0 1 0 1 0 1 0 0 0 1 0 1/9 bias 1/8 bias 1/6 bias 1/8 bias 1/8 bias 1 1/7 bias 1/6 bias 1/5 bias 1/6 bias 1/6 bias e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 11100000
sed1565 series epson 8C51 sed1565 series ? the sequence for cursor display figure 24 end this command releases the read/modify/write mode, and returns the column address to the address it was at when the mode was entered. figure 25 reset this command initializes the display start line, the column address, the page address, the common output mode, the v 5 voltage regulator internal resistor ratio, the electronic volume, and the static indicator are reset, and the read/modify/ write mode and test mode are released. there is no impact on the display data ram. see the function explanation in reset for details. the reset operation is performed after the reset command is entered. the initialization when the power supply is applied must be done through applying a reset signal to the res terminal. the reset command must not be used instead. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 11101110 e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 11100010 page address set column address set dummy read data read data write data process end yes no change complete? read/modify/write n n+m ?? n+3 n+2 n+1 n column address read/modify/write mode set end return
sed1565 series 8C52 epson common output mode select this command can select the scan direction of the com output terminal. for details, see the function explanation in common output mode select circuit. power controller set this command sets the power supply circuit functions. see the function explanation in the power supply circuit, for details v 5 voltage regulator internal resistor ratio set this command sets the v 5 voltage regulator internal resistor ratio. for details, see the function explanation is the power supply circuits. the electronic volume (double byte command) this command makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal drive voltage v 5 through the output from the voltage regulator circuits of the internal liquid crystal power supply. this command is a two byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other. ? the electronic volume mode set when this command is input, the electronic volume register set command becomes enabled. once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 selected mode 0 1 0 0 0 1 0 1 0 booster circuit: off 1 booster circuit: on 0 voltage regulator circuit: off 1 voltage regulator circuit: on 0 voltage follower circuit: off 1 voltage follower circuit: on [translators note: the abbreviations explained within these parentheses for v and v/f have been written out in the english translation and are therefore no longer necessary.] e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 rb/ra ratio 0 1 0 0 0 1 0 0 0 0 0 small 001 010 110 1 1 1 large e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 10000001 e r/w selected mode a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 sed1565* ** sed1566* ** sed1567* ** sed1568* ** sed1569* ** 0 1 0 11000* * * normal com0 ? com63 com0 ? com47 com0 ? com31 com0 ? com53 com0 ? com51 1 reverse com63 ? com0 com47 ? com0 com31 ? com0 com53 ? com0 com51 ? com0 * disabled bit
sed1565 series epson 8C53 sed1565 series ? electronic volume register set by using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage v 5 assumes one of the 64 voltage levels. when this command is input, the electronic volume mode is released after the electronic volume register has been set. when the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0) ? the electronic volume register set sequence figure 26 static indicator (double byte command) this command controls the static drive system indicator display. the static indicator display is controlled by this command only, and is independent of other display control commands. this is used when one of the static indicator liquid crystal drive electrodes is connected to the fr terminal, and the other is connected to the frs terminal. a different pattern is recommended for the static indicator electrodes than for the dynamic drive electrodes. if the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes. the static indicator on command is a double byte command paired with the static indicator register set command, and thus one must execute one after the other. (the static indicator off command is a single byte command.) ? static indicator on/off when the static indicator on command is entered, the static indicator register set command is enabled. once the static indicator on command has been entered, no other command aside from the static indicator register set command can be used. this mode is cleared when data is set in the register by the static indicator register set command. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 | v 5 | 0 1 0 * * 0 0 0 0 0 1 small 0 1 0 * *000010 0 1 0 * *000011 0 1 0 * *111110 0 1 0 * * 1 1 1 1 1 1 large * inactive bit e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 static indicator 0 1 0 10101100 off 1on electronic volume mode set electronic volume register set electronic volume mode clear yes no changes complete?
sed1565 series 8C54 epson ? static indicator register set this command sets two bits of data into the static indicator register, and is used to set the static indicator into a blinking mode. ? static indicator register set sequence figure 27 power save (compound command) when the display all points on is performed while the display is in the off mode, the power saver mode is entered, thus greatly reducing power consumption. the power saver mode has two different modes: the sleep mode and the standby mode. when the static indicator is off, it is the sleep mode that is entered. when the static indicator is on, it is the standby mode that is entered. in the sleep mode and in the standby mode, the display data is saved as is the operating mode that was in effect before the power saver mode was initiated, and the mpu is still able to access the display data ram. refer to figure 26 for power save off sequence. figure 28 static indicator off power saver (compound command) static indicator on standby mode standby mode cancel sleep mode sleep mode cancel power save off (compound command) display all points off command static indicator on (2 bytes command) power save off (display all points off command) static indicator mode set static indicator register set static indicator mode clear yes no changes complete? e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 indicator display state 0 1 0 ******00off 0 1 on (blinking at approximately one second intervals) 1 0 on (blinking at approximately 0.5 second intervals) 1 1 on (constantly on) * disabled bit
sed1565 series epson 8C55 sed1565 series ? sleep mode this stops all operations in the lcd display system, and as long as there are no accesses from the mpu, the consumption current is reduced to a value near the static current. the internal modes during sleep mode are as follows: 1 the oscillator circuit and the lcd power supply circuit are halted. 2 all liquid crystal drive circuits are halted, and the segment in common drive outputs output a v dd level. ? standby mode the duty lcd display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. the internal modes are in the following states during standby mode. 1 the lcd power supply circuits are halted. the oscillator circuit continues to operate. 2 the duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs output a v dd level. the static drive system does not operate. when a reset command is performed while in standby mode, the system enters sleep mode. * when an external power supply is used, it is recommended that the functions of the external power supply circuit be stopped when the power saver mode is started. for example, when the various levels of liquid crystal drive voltage are provided by external resistive voltage dividers, it is recommended that a circuit be added in order to cut the electrical current flowing through the resistive voltage divider circuit when the power saver mode is in effect. the sed1565 series chips have a liquid crystal display blanking control terminal dof. this terminal enters an l state when the power saver mode is launched. using the output of dof, it is possible to stop the function of an external power supply circuit. * when the master is turned on, the oscillator circuit is operable immediately after the powering on. nop non-operation command test this is a command for ic chip testing. please do not use it. if the test command is used by accident, it can be cleared by applying a l signal to the res input by the reset command or by using an nop. note: the sed1565 series chips maintain their operating modes until something happens to change them. consequently, excessive external noise, etc., can change the internal modes of the sed1565 series chip. thus in the packaging and system design it is necessary to suppress the noise or take measure to prevent the noise from influencing the chip. moreover, it is recommended that the operating modes be refreshed periodically to prevent the effects of unanticipated noise. e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101111**** * inactive bit e r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 11100011
sed1565 series 8C56 epson command code command a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function (1) display on/off 0 1 0 1 0 1 0 1 1 1 0 lcd display on/off 1 0: off, 1: on (2) display start line set 0 1 0 0 1 display start address sets the display ram display start line address (3) page address set 0 1 0 1 0 1 1 page address sets the display ram page address (4) column address 0 1 0 0 0 0 1 most significant sets the most significant 4 bits set upper bit column address of the display ram column address. column address 0 1 0 0 0 0 0 least significant sets the least significant 4 bits of set lower bit column address the display ram column address. (5) status read 0 0 1 status 0 0 0 0 reads the status data (6) display data write 1 1 0 write data writes to the display ram (7) display data read 1 0 1 read data reads from the display ram (8) adc select 0 1 0 1 0 1 0 0 0 0 0 sets the display ram address 1 seg output correspondence 0: normal, 1: reverse (9) display normal/ 0 1 0 1 0 1 0 0 1 1 0 sets the lcd display normal/ reverse 1 reverse 0: normal, 1: reverse (10) display all points 0 1 0 1 0 1 0 0 1 0 0 display all points on/off 1 0: normal display 1: all points on (11) lcd bias set 0 1 0 1 0 1 0 0 0 1 0 sets the lcd drive voltage 1 bias ratio sed1565* ** ....... 0: 1/9, 1: 1/7 sed1566* ** /sed1568* ** /sed1569* ** ...... 0: 1/8, 1: 1/6 sed1567* ** ....... 0: 1/6, 1: 1/5 (12) read/modify/write 0 1 0 1 1 1 0 0 0 0 0 column address increment at write: +1 at read: 0 (13) end 0 1 0 1 1 1 0 1 1 1 0 clear read/modify/write (14) reset 0 1 0 1 1 1 0 0 0 1 0 internal reset (15) common output 0 1 0 1 1 0 0 0 * * * select com output scan mode select 1 direction 0: normal direction, 1: reverse direction (16) power control set 0 1 0 0 0 1 0 1 operating select internal power mode supply operating mode (17) v 5 voltage 0 1 0 0 0 1 0 0 resistor ratio select internal resistor ratio regulator internal (rb/ra) mode resistor ratio set (18) electronic volume 0 1 0 1 0 0 0 0 0 0 1 mode set electronic volume 0 1 0 * * electronic volume value set the v 5 output voltage register set electronic volume register (19) static indicator 0 1 0 1 0 1 0 1 1 0 0 0: off, 1: on on/off 1 static indicator 0 1 0 * * * * * * mode set the flashing mode register set (20) power saver display off and display all points on compound command (21) nop 0 1 0 1 1 1 0 0 0 1 1 command for non-operation (22) test 0 1 0 1 1 1 1 * * * * command for ic test. do not use this command (note) *: disabled data table 16 table of sed1565 series commands
sed1565 series epson 8C57 sed1565 series command description instruction setup: reference (reference) (1) initialization note: with this ic, when the power is applied, lcd driving non-selective potentials v 2 and v 3 (seg pin) and v 1 and v 4 (com pin) are output through the lcd driving output pins seg and com. when electric charge is remaining in the smoothing capacitor connecting between the lcd driving voltage output pins (v 1 ~ v 5 ) and the v dd pin, the picture on the display may become totally dark instantaneously when the power is turned on. to avoid occurrence of such a failure, we recommend the following flow when turning on the power. 1 when the built-in power is being used immediately after turning on the power: turn on the v dd -v ss power keeping the res pin = ?? when the power is stabilized initialized state (default) *1 this concludes the initialization function setup by command input (user setup) (11) lcd bias setting *2 (8) adc selection *3 (15) common output state selection *4 function setup by command input (user setup) (17) setting the built-in resistance radio for regulation of the v 5 voltage *5 (18) electronic volume control *6 function setup by command input (user setup) (16) power control setting *7 release the reset state. (res pin = ?? (in case of sed1565d bb , sed1566d bb , sed1567d bb , sed1568d bb and sed1569d bb ) arrange to execute all the procedures from releasing the reset state through setting the power control within 5ms. (in case of other models) execute the procedures from turning on the power to setting the power control in 5ms. * the target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. therefore, we suggest you to conduct an operation check using the actual equipment. notes: refer to respective sections or paragraphs listed below. *1: description of functions; resetting circuit *2: command description; lcd bias setting *3: command description; adc selection *4: command description; common output state selection *5: description of functions; power circuit & command description; setting the built-in resistance radio for regulation of the v 5 voltage *6: description of functions; power circuit & command description; electronic volume control *7: description of functions; power circuit & command description; power control setting
sed1565 series 8C58 epson command description instruction setup: reference (reference) 2 when the built-in power is not being used immediately after turning on the power: * the target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. therefore, we suggest you to conduct an operation check using the actual equipment. notes: refer to respective sections or paragraphs listed below. *1: description of functions; resetting circuit *2: command description; lcd bias setting *3: command description; adc selection *4: command description; common output state selection *5: description of functions; power circuit & command description; setting the built-in resistance radio for regulation of the v 5 voltage *6: description of functions; power circuit & command description; electronic volume control *7: description of functions; power circuit & command description; power control setting *8: the power saver on state can either be in sleep state or stand-by state. command description; power saver start (multiple commands) turn on the v dd -v ss power keeping the res pin = ?? when the power is stabilized power saver start (multiple commands) *8 power saver off *8 initialized state (default) *1 this concludes the initialization function setup by command input (user setup) (11) lcd bias setting *2 (8) adc selection *3 (15) common output state selection *4 function setup by command input (user setup) (17) setting the built-in resistance radio for regulation of the v 5 voltage *5 (18) electronic volume control *6 function setup by command input (user setup) (16) power control setting *7 release the reset state. (res pin = ?? (in case of sed1565d bb , sed1566d bb , sed1567d bb , sed1568d bb and sed1569d bb ) arrange to start the power saver within 5ms after releasing the reset state. (in case of other models) execute the procedures from turning on the power to setting the power control in 5ms. arrange to start power control setting within 5ms after turning off the power saver.
sed1565 series epson 8C59 sed1565 series (2) data display (3) power off *14 ? in case of sed1565d bb , sed1566d bb , sed1567d bb , sed1568d bb and sed1569d bb , ? in case of other models, notes: reference items *14: the logic circuit of this ics power supply v dd - v ss controls the driver of the lcd power supply v dd - v 5 . so, if the power supply v dd - v ss is cut off when the lcd power supply v dd - v 5 has still any residual voltage, the driver (com. seg) may output any uncontrolled voltage. when turning off the power, observe the following basic procedures: ? after turning off the internal power supply, make sure that the potential v 5 ~ v 1 has become below the threshold voltage of the lcd panel, and then turn off this ics power supply (v dd - v ss ). 6. description of function, 6.7 power circuit *15: after inputting the power save command, be sure to reset the function using the res terminal until the power supply v dd - v ss is turned off. 7. command description (20) power save *16: after inputting the power save command, do not reset the function using the res terminal until the power supply v dd - v ss is turned off. 7. command description (20) power save end of data display end of initialization function setup by command input (user setup) (2) display start line set *9 (3) page address set *10 (4) column address set *11 function setup by command input (user setup) (1) display on/off *13 function setup by command input (user setup) (6) display data write *12 reset active (res pin = ?? optional status function setup by command input (user setup) (20) power save *15 v dd ?v ss power off set the time ( t l ) from reset active to turning off the v dd - v ss power (v dd - v ss = 1.8 v) longer than the time ( t h ) when the potential of v 5 ~ v 1 becomes below the threshold voltage (approximately 1 v) of the lcd panel. for t h , refer to the of this event. when t h is too long, insert a resistor between v 5 and v dd to reduce it. v dd ?v ss power off optional status function setup by command input (user setup) (20) power save *15 set the time ( t l ) from power save to turning off the v dd - v ss power (v dd - v ss = 1.8 v) longer than the time ( t h ) when the potential of v 5 ~ v 1 becomes below the threshold voltage (approximately 1v) of the lcd panel. ? t h is determined depending on the voltage regulator external resistors ra and rb and the time constant of v 5 ~ v 1 smoothing capacity c2. ?when an internal resistor is used, it is recommended to insert a resistor r between v dd and v 5 to reduce t h . notes: reference items *9: command description; display start line set *10: command description; page address set *11: command description; column address set *12: command description; display data write *13: command description; display on/off avoid displaying all the data at the data display start (when the display is on) in white.
sed1565 series 8C60 epson refresh it is recommended to turn on the refresh sequence regularly at a specified interval. reset command or nop command refresh sequence refreshing of dram set all commands to the ready state precautions on turning off the power ? in case of sed1565d bb , sed1566d bb , sed1567d bb , sed1568d bb and sed1569d bb , observe paragraph 1) as the basic rule. 1) power save (the lcd powers (v dd - v 5 ) are off.) ? reset input ? power (v dd - v ss ) off ? observe t l > t h . ? when t l < t h , an irregular display may occur. set t l on the mpu according to the software. t h is determined according to the external capacity c 2 (smoothing capacity of v 5 ~ v 1 ) and the drivers discharging capacity. t l 1.8 v since the power (v dd -v ss ) is cut off, the output comes not to be fixed. about 1 v: below vth of the lcd panel t h for t h , see figure 29. v 1 v 2 v 3 v 4 v 5 com seg power save power off reset v dd v dd v dd res
sed1565 series epson 8C61 sed1565 series 2) reset (the lcd powers (v dd - v ss ) are off.) ? power (v dd - v ss ) off ? observe t l > t h . ? when t l < t h , an irregular display may occur. for t l , make the power (v dd - v ss ) falling characteristics longer or consider any other method. t h is determined according to the external capacity c 2 (smoothing capacity of v 5 to v 1 ) and the drivers discharging capacity. v 5 voltage falling (discharge) time ( t h ) after the process of operation ? power save ? reset. v 5 voltage falling (discharge) time ( t h ) after the process of operation ? reset. figure 29 t l 1.8 v since the power (v dd -v ss ) is cut off, the output comes not be fixed. about 1 v: below vth of the lcd panel t h for t h , see figure 29. v 1 v 2 v 3 v 4 v 5 com seg power off reset v dd v dd v dd res 100 50 0 0.5 c2: v 1 to v 5 capacity (uf) 1.0 1.8 v dd -v ss (v) v 5 voltage falling time (msec) 2.4 3.0 4.0 5.0
sed1565 series 8C62 epson ? in case of other models than the above power save (the lcd powers (v dd - v ss ) are off.) -> power (v dd - v ss ) off ? observe t l > t h . ? when t l < t h , an irregular display may occur. set t l on the mpu according to the software. t h is determined according to the external capacity c (smoothing capacity of v 5 to v 1 ) and the external resisters ra + rb (for v 5 voltage regulation) t l 1.8 v since the power (v dd -v ss ) is cut off, the output comes not be fixed. about 1 v: below vth of the lcd panel t h t h is determined depending on the time constant of (ra + rb) c. v 1 v 2 v 3 v 4 v 5 com seg power save power off v dd
sed1565 series epson 8C63 sed1565 series v dd v dd v ss2 , v 1 to v 4 v 5 , v out v cc gnd v ss sed1565 series chip side system (mpu) side absolute maximum ratings unless otherwise noted, v ss = 0 v parameter symbol conditions unit power supply voltage v dd C0.3 to +7.0 v power supply voltage (2) v ss2 C7.0 to +0.3 v (v dd standard) with triple step-up C6.0 to +0.3 with quad step-up C4.5 to +0.3 power supply voltage (3) (v dd standard) v 5 , v out C18.0 to +0.3 v power supply voltage (4) (v dd standard) v 1 , v 2 , v 3 , v 4 v 5 to +0.3 v input voltage v in C0.3 to v dd + 0.3 v output voltage v o C0.3 to v dd + 0.3 v operating temperature t opr C40 to +85 c storage temperature tcp t str C55 to +100 bare chip C55 to +125 c figure 30 notes and cautions 1. the v ss2 , v 1 to v 5 and v out are relative to the v dd = 0v reference. 2. insure that the voltage levels of v 1 , v 2 , v 3 , and v 4 are always such that v dd 3 v 1 3 v 2 3 v 3 3 v 4 3 v 5 . 3. permanent damage to the lsi may result if the lsi is used outside of the absolute maximum ratings. moreover, it is recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the lsi outside of these conditions may not only result in malfunctions of the lsi, but may have a negative impact on the lsi reliability as well. table 17
sed1565 series 8C64 epson dc characteristics unless otherwise specified, v ss = 0 v, v dd = 3.0 v 10%, ta = C40 to 85 c item symbol condition rating units applicable min. typ. max. pin operating recom- v dd 2.7 3.3 v v dd * 1 voltage (1) mended voltage possible 1.8 5.5 v v dd * 1 operating voltage operating recom- v ss2 (relative to v dd ) C3.3 C2.7 v v ss2 voltage (2) mended voltage possible v ss2 (relative to v dd ) C6.0 C1.8 v v ss2 operating voltage operating possible v 5 (relative to v dd ) C16.0 C4.5 v v 5 *2 voltage (3) operating voltage possible v 1 , v 2 (relative to v dd ) 0.4 v 5 v dd vv 1 , v 2 operating voltage possible v 3 , v 4 (relative to v dd )v 5 0.6 v 5 vv 3 , v 4 operating voltage high-level input v ihc 0.8 v dd v dd v*3 voltage low-level input v ilc v ss 0.2 v dd v*3 voltage high-level output v ohc i oh = C0.5 ma 0.8 v dd v dd v*4 voltage low-level output v olc i ol = 0.5 ma v ss 0.2 v dd v*4 voltage input leakage i li v in = v dd or v ss C1.0 1.0 m a*5 current output leakage i lo C3.0 3.0 m a*6 current liquid crystal driver r on ta = 25 cv 5 = C14.0 v 2.0 3.5 k w segn on resistance (relative to v dd )v 5 = C8.0 v 3.2 5.4 k w comn *7 static consumption i ssq 0.01 5 m av ss , v ss2 current output leakage i 5q v 5 = C18.0 v 0.01 15 m av 5 current (relative to v dd ) input terminal c in ta = 25 c f = 1 mhz 5.0 8.0 pf capacitance oscillator internal f osc ta = 25 c 18 22 26 khz *8 frequency oscillator external f cl sed1565 * ** /1567 * ** 18 22 26 khz cl input internal f osc ta = 25 c 27 33 39 khz *8 oscillator external f cl sed1566 * ** /1568 * ** / 14 17 20 khz cl input 1569 * ** table 18
sed1565 series epson 8C65 sed1565 series item symbol condition rating units applicable min. typ. max. pin input voltage v ss2 with triple C6.0 C1.8 v v ss2 (relative to v dd ) v ss2 with quad C4.5 C1.8 v v ss2 (relative to v dd ) supply step-up v out (relative to v dd ) C18.0 v v out output voltage circuit voltage regulator v out (relative to v dd ) C18.0 C6.0 v v out circuit operating voltage voltage follower v 5 (relative to v dd ) C16.0 C4.5 v v 5 *9 circuit operating voltage base voltage v reg0 ta = 25 c C0.05%/ c C2.04 C2.10 C2.16 v *10 v reg1 (relative to v dd ) C0.2%/ c C4.65 C4.9 C5.15 v *10 internal power table 19
sed1565 series 8C66 epson ? dynamic consumption current (1), during display, with the internal power supply off current consumed by total ics when an external power supply is used. ? dynamic consumption current (2), during display, with the internal power supply on ta = 25 c item symbol condition rating units notes min. typ. max. sed1565 * ** i dd (1) v dd = 5.0 v, v 5 C v dd = C11.0 v 23 38 m a *11 v dd = 3.0 v, v 5 C v dd = C11.0 v 21 35 sed1566 * ** v dd = 3.0 v, v 5 C v dd = C11.0 v 17 29 v dd = 5.0 v, v 5 C v dd = C8.0 v 14 24 v dd = 3.0 v, v 5 C v dd = C8.0 v 12 20 sed1567 * ** v dd = 5.0 v, v 5 C v dd = C8.0 v 11 18 v dd = 3.0 v, v 5 C v dd = C8.0 v 10 17 sed1568 * ** /v dd = 5.0 v, v 5 C v dd = C8.0 v 15 25 sed1569 * ** v dd = 3.0 v, v 5 C v dd = C8.0 v 13 22 table 21 display pattern checker ta = 25 c item symbol condition rating units notes min. typ. max. sed1565 * ** i dd (1) v dd = 5.0 v, v 5 C v dd = C11.0 v 18 30 m a *11 v dd = 3.0 v, v 5 C v dd = C11.0 v 16 27 sed1566 * ** v dd = 3.0 v, v 5 C v dd = C11.0 v 13 22 v dd = 5.0 v, v 5 C v dd = C8.0 v 11 19 v dd = 3.0 v, v 5 C v dd = C8.0 v 9 15 sed1567 * ** v dd = 5.0 v, v 5 C v dd = C8.0 v 8 13 v dd = 3.0 v, v 5 C v dd = C8.0 v 7 12 sed1568 * ** /v dd = 5.0 v, v 5 C v dd = C8.0 v 12 20 sed1569 * ** v dd = 3.0 v, v 5 C v dd = C8.0 v 10 17 table 20 display pattern off ta = 25 c item symbol condition rating units notes min. typ. max. sed1565 * ** i dd (2) v dd = 5.0 v, triple step-up voltage. normal mode 67 112 m a *12 v 5 C v dd = C11.0 v high-power mode 114 190 v dd = 3.0 v, quad step-up voltage. normal mode 81 135 v 5 C v dd = C11.0 v high-power mode 138 230 sed1566 * ** v dd = 5.0 v, double step-up voltage. normal mode 3559 v 5 C v dd = C8.0 v high-power mode 64 107 v dd = 3.0 v, triple step-up voltage. normal mode 4372 v 5 C v dd = C8.0 v high-power mode 84 140 v dd = 3.0 v, quad step-up voltage. normal mode 72 121 v 5 C v dd = C11.0 v high-power mode 128 214 sed1567 * ** v dd = 5.0 v, double step-up voltage. normal mode 2644 v 5 C v dd = C8.0 v high-power mode 60 100 v dd = 3.0 v, triple step-up voltage. normal mode 2949 v 5 C v dd = C8.0 v high-power mode 73 122 sed1568 * ** / v dd = 5.0 v, double step-up voltage. normal mode 3762 sed1569 * ** v 5 C v dd = C8.0 v high-power mode 67 112 v dd = 3.0 v, triple step-up voltage. normal mode 4677 v 5 C v dd = C8.0 v high-power mode 87 145 table 22 display pattern off
sed1565 series epson 8C67 sed1565 series ? consumption current at time of power saver mode, v ss = 0 v, v dd = 3.0 v 10% ta = 25 c item symbol condition rating units notes min. typ. max. sed1565 * ** i dd (2) v dd = 5.0 v, triple step-up voltage. normal mode 81 135 m a *12 v 5 C v dd = C11.0 v high-power mode 127 212 v dd = 3.0 v, quad step-up voltage. normal mode 96 160 v 5 C v dd = C11.0 v high-power mode 153 255 sed1566 * ** v dd = 5.0 v, double step-up voltage. normal mode 4169 v 5 C v dd = C8.0 v high-power mode 71 119 v dd = 3.0 v, triple step-up voltage. normal mode 5185 v 5 C v dd = C8.0 v high-power mode 92 154 v dd = 3.0 v, quad step-up voltage. normal mode 85 142 v 5 C v dd = C11.0 v high-power mode 142 237 sed1567 * ** v dd = 5.0 v, double step-up voltage. normal mode 3253 v 5 C v dd = C8.0 v high-power mode 62 103 v dd = 3.0 v, triple step-up voltage. normal mode 4473 v 5 C v dd = C8.0 v high-power mode 89 148 sed1568 * ** / v dd = 5.0 v, double step-up voltage. normal mode 4474 sed1569 * ** v 5 C v dd = C8.0 v high-power mode 74 127 v dd = 3.0 v, triple step-up voltage. normal mode 5490 v 5 C v dd = C8.0 v high-power mode 95 159 table 23 display pattern checker ta = 25 c item symbol condition rating units notes min. typ. max. sleep mode sed1565 * ** i dds1 0.01 5 m a standby mode sed1565 * ** i dds2 48 m a sleep mode sed1566 * ** i dds1 0.01 5 m a standby mode sed1566 * ** i dds2 48 m a sleep mode sed1567 * ** i dds1 0.01 5 m a standby mode sed1567 * ** i dds2 36 m a sleep mode sed1568 * ** /i dds1 0.01 5 m a sed1569 * ** standby mode sed1568 * ** /i dds2 48 m a sed1569 * ** table 24 tbd: to be determined
sed1565 series 8C68 epson reference data 1 ? dynamic consumption current (1) during lcd display using an external power supply figure 31 figure 32 40 30 20 10 0 02468 v dd [v] i dd (1) (i ss + i 5 ) [ a] conditions: internal power supply off external power supply in use sed1565/sed1566 (?1.0v): v 5 ?v dd = ?1.0 v sed1566 (?.0v)/sed1567: v 5 ?v dd = ?.0 v display pattern: off ta = 25 c note: *11 sed1565 sed1566 (?1.0v) sed1566 (?.0v) sed1567 sed1568/sed1569 (?.0v) 40 30 20 10 0 02468 v dd [v] i dd (1) (i ss + i 5 ) [ a] internal power supply off external power supply in use sed1565/sed1566 (?1.0v): v 5 ?v dd = ?1.0 v sed1566 (?.0v)/sed1567: v 5 ?v dd = ?.0 v display pattern: checker ta = 25 c note: *11 conditions: sed1565 sed1566 (?.0v) sed1568/sed1569 (?.0v) sed1566 (?1.0v ) sed1567
sed1565 series epson 8C69 sed1565 series reference data 2 ? dynamic consumption current (2) during lcd display using the internal power supply figure 33 figure 34 140 120 100 80 60 40 20 0 02468 v dd [v] i dd (2) [ a] conditions: internal power supply on sed1565/sed1566 ( 4, ?1.0v): 4 step-up voltage: v 5 ?v dd = ?1.0 v sed1566 ( 3, ?.0v)/sed1567: 3 step-up voltage: v 5 ?v dd = ?.0 v normal mode display pattern: off ta = 25 c note: *12 sed1565 sed1566 ( 4, ?1.0v) sed1566 ( 3, ?.0v) sed1568/sed1569 ( 3, ?.0v) sed1568/sed1569 ( 2, ?.0v) sed1567 120 100 80 60 40 20 0 02468 v dd [v] i dd (2) [ a] internal power supply on sed1565/sed1566 ( 4, ?1.0v): 4 step-up voltage: v 5 ?v dd = ?1.0 v sed1566 ( 3, ?.0v)/sed1567: 3 step-up voltage: v 5 ?v dd = ?.0 v normal mode display pattern: checker ta = 25 c note: *12 conditions: sed1565 sed1566 ( 4, ?1.0v) sed1566 ( 3, ?.0v) sed1568/sed1569 ( 2, ?.0v) sed1568/sed1569 ( 3, ?.0v) sed1567
sed1565 series 8C70 epson reference data 3 ? dynamic consumption current (3) during access figure 35 reference data 4 ? operating voltage range of v ss and v 5 systems figure 36 sed1565 series note: *2 ?0 ?6 ?.2 ?.5 1.8 3.0 5.5 02 v dd [v] 468 ?5 ?0 v 5 -v dd [v] ? 0 operating range 10 1 0.1 i dd (3)[ma] 0.01 0.001 0.01 0.1 f cyc [mhz] 110 this figure indicates the consumption current while the checker pattern is constantly written through f cyc . if there is no access, then only (1) remains. conditions: internal power supply off, external power supply used sed1565: v dd ?v ss = 3.0 v, v 5 =?1.0 v sed1566/sed1567: v dd ?v ss = 3.0 v, v 5 =?.0 v ta = 25 c sed1565 sed1566 sed1567 sed1568/sed1569
sed1565 series epson 8C71 sed1565 series ? the relationship between oscillator frequency f osc , display clock frequency f cl and the liquid crystal frame rate frequency f fr references for items market with * *1 while a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the mpu is being accessed. *2 the operating voltage range for the v dd system and the v 5 system is as shown in figure 33. this applies when the external power supply is being used. *3 the a0, d0 to d5, d6 (scl), d7 (si), rd (e), wr (r/w), cs1, cs2, cls, cl, fr, m/s, c86, p/s, dof, res, irs, and hpm terminals. *4 the d0 to d7, fr, frs, dof, and cl terminals. *5 the a0, rd (e), wr (r/w), cs1, cs2, cls, m/s, c86, p/s, res, irs, and hpm terminals. *6 applies when the d0 to d5, d6 (scl), d7 (si), cl, fr, and dof terminals are in a high impedance state. *7 these are the resistance values for when a 0.1 v voltage is applied between the output terminal segn or comn and the various power supply terminals (v 1 , v 2 , v 3 , and v 4 ). these are specified for the operating voltage (3) range. r on = 0.1 v/ d i (where d i is the current that flows when 0.1 v is applied while the power supply is on.) *8 see table 9-7 for the relationship between the oscillator frequency and the frame rate frequency. *9 the v 5 voltage regulator circuit regulates within the operating voltage range of the voltage follower. *10 this is the internal voltage reference supply for the v 5 voltage regulator circuit. in the sed1565 series chips, the temperature range can come in three types as v reg options: (1) approximately C0.05%/ c, (2) C 0.2%/ c, and (3) external input. *11, 12 it indicates the current consumed on ics alone when the internal oscillator circuit and display are turned on. the sed1565 is 1/9 biased, sed1566 is 1/8 biased and sed1567 is 1/6 biased. does not include the current due to the lcd panel capacity and wiring capacity. applicable only when there is no access from the mpu. *12 it is the value on a model having the v reg option temperature gradient is C0.05%/ c when the v 5 voltage regulator internal resistor is used. table 25 item f cl f fr sed1565 * ** when the internal oscillator circuit is used f osc f osc ____ _____ 44 65 when the internal oscillator circuit is not used external input (f cl )f cl ____ 260 sed1566 * ** when the internal oscillator circuit is used f osc f osc ____ _____ 88 49 when the internal oscillator circuit is not used external input (f cl )f cl ____ 196 sed1567 * ** when the internal oscillator circuit is used f osc f osc ____ _____ 88 33 when the internal oscillator circuit is not used external input (f cl )f cl ____ 264 sed1568 * ** when the internal oscillator circuit is used f osc f osc ____ _____ 88 55 when the internal oscillator circuit is not used external input (f cl )f cl ____ 220 sed1569 * ** when the internal oscillator circuit is used f osc f osc ____ _____ 88 53 when the internal oscillator circuit is not used external input (f cl )f cl ____ 212 (f fr is the liquid crystal alternating current period, and not the fr signal period.)
sed1565 series 8C72 epson timing characteristics system bus read/write characteristics 1 (for the 8080 series mpu) figure 37 (v dd = 4.5 v to 5.5 v, ta = C40 to 85 c ) item signal symbol condition rating units min max address hold time a0 t ah8 0ns address setup time t aw8 0ns system cycle time a0 t cyc8 166 ns control l pulse width (wr) wr t cclw 30 ns control l pulse width (rd) rd t cclr 70 ns control h pulse width (wr) wr t cchw 30 ns control h pulse width (rd) rd t cchr 30 ns data setup time d0 to d7 t ds8 30 ns address hold time t dh8 10 ns rd access time t acc8 c l = 100 pf 70 ns output disable time t oh8 550ns table 26 a0 cs1 (cs2="1") wr, rd d0 to d7 (write) d0 to d7 (read) t acc8 t oh8 t ds8 t cyc8 t ah8 t aw8 t cclr , t cclw t cchr , t cchw t ds8
sed1565 series epson 8C73 sed1565 series (v dd = 2.7 v to 4.5 v, ta = C40 to 85 c ) item signal symbol condition rating units min max address hold time a0 t ah8 0ns address setup time t aw8 0ns system cycle time a0 t cyc8 300 ns control l pulse width (wr) wr t cclw 60 ns control l pulse width (rd) rd t cclr 120 ns control h pulse width (wr) wr t cchw 60 ns control h pulse width (rd) rd t cchr 60 ns data setup time d0 to d7 t ds8 40 ns address hold time t dh8 15 ns rd access time t acc8 c l = 100 pf 140 ns output disable time t oh8 10 100 ns table 27 (v dd = 1.8 v to 2.7 v, ta = C40 to 85 c ) item signal symbol condition rating units min max address hold time a0 t ah8 0ns address setup time t aw8 0ns system cycle time a0 t cyc8 1000 ns control l pulse width (wr) wr t cclw 120 ns control l pulse width (rd) rd t cclr 240 ns control h pulse width (wr) wr t cchw 120 ns control h pulse width (rd) rd t cchr 120 ns data setup time d0 to d7 t ds8 80 ns address hold time t dh8 30 ns rd access time t acc8 c l = 100 pf 280 ns output disable time t oh8 10 200 ns table 28 *1 the input signal rise time and fall time ( t r , t f ) is specified at 15 ns or less. when the system cycle time is extremely fast, ( t r + t f ) ( t cyc8 C t cclw C t cchw ) for ( t r + t f ) ( t cyc8 C t cclr C t cchr ) are specified. *2 all timing is specified using 20% and 80% of v dd as the reference. *3 t cclw and t cclr are specified as the overlap between cs1 being l (cs2 = h) and wr and rd being at the l level.
sed1565 series 8C74 epson (v dd = 4.5 v to 5.5 v, ta = C40 to 85 c ) item signal symbol condition rating units min max address hold time a0 t ah6 0ns address setup time t aw6 0ns system cycle time a0 t cyc6 166 ns data setup time d0 to d7 t ds6 30 ns data hold time t dh6 10 ns access time t acc6 c l = 100 pf 70 ns output disable time t oh6 10 50 ns enable h pulse read e t ewhr 70 ns time write t ewhw 30 ns enable l pulse read e t ewlr 30 ns time write t ewlw 30 ns table 29 system bus read/write characteristics 2 (6800 series mpu) figure 38 a0 r/w cs1 (cs2="1") e d0 to d7 (write) d0 to d7 (read) t acc6 t oh6 t ds6 t cyc6 t ah6 t aw6 t ewhr , t ewhw t ewlr , t ewlw t dh6
sed1565 series epson 8C75 sed1565 series (v dd = 2.7 v to 4.5 v, ta = C40 to 85 c ) item signal symbol condition rating units min max address hold time a0 t ah6 0ns address setup time t aw6 0ns system cycle time a0 t cyc6 300 ns data setup time d0 to d7 t ds6 40 ns data hold time t dh6 15 ns access time t acc6 c l = 100 pf 140 ns output disable time t oh6 10 100 ns enable h pulse read e t ewhr 120 ns time write t ewhw 60 ns enable l pulse read e t ewlr 60 ns time write t ewlw 60 ns table 30 (v dd = 1.8 v to 2.7 v, ta = C40 to 85 c ) item signal symbol condition rating units min max address hold time a0 t ah6 0ns address setup time t aw6 0ns system cycle time a0 t cyc6 1000 ns data setup time d0 to d7 t ds6 80 ns data hold time t dh6 30 ns access time t acc6 c l = 100 pf 280 ns output disable time t oh6 10 200 ns enable h pulse read e t ewhr 240 ns time write t ewhw 120 ns enable l pulse read e t ewlr 120 ns time write t ewlw 120 ns table 31 *1 the input signal rise time and fall time ( t r , t f ) is specified at 15 ns or less. when the system cycle time is extremely fast, ( t r + t f ) ( t cyc6 C t ewlw C t ewhw ) for ( t r + t f ) ( t cyc6 C t ewlr C t ewhr ) are specified. *2 all timing is specified using 20% and 80% of v dd as the reference. *3 t ewlw and t ewlr are specified as the overlap between cs1 being l (cs2 = h) and e.
sed1565 series 8C76 epson (v dd = 4.5 v to 5.5 v, ta = C40 to 85 c ) item signal symbol condition rating units min max serial clock period scl t scyc 200 ns scl h pulse width t shw 75 ns scl l pulse width t slw 75 ns address setup time a0 t sas 50 ns address hold time t sah 100 ns data setup time si t sds 50 ns data hold time t sdh 50 ns cs-scl time cs t css 100 ns t csh 100 ns table 32 the serial interface figure 39 t css t csh t sah t shw t sdh t sds t slw t f t r t scyc t sas cs1 (cs2="1") a0 scl si
sed1565 series epson 8C77 sed1565 series (v dd = 2.7 v to 4.5 v, ta = C40 to 85 c ) item signal symbol condition rating units min max serial clock period scl t scyc 250 ns scl h pulse width t shw 100 ns scl l pulse width t slw 100 ns address setup time a0 t sas 150 ns address hold time t sah 150 ns data setup time si t sds 100 ns data hold time t sdh 100 ns cs-scl time cs t css 150 ns t csh 150 ns table 33 (v dd = 1.8 v to 2.7 v, ta = C40 to 85 c ) item signal symbol condition rating units min max serial clock period scl t scyc 400 ns scl h pulse width t shw 150 ns scl l pulse width t slw 150 ns address setup time a0 t sas 250 ns address hold time t sah 250 ns data setup time si t sds 150 ns data hold time t sdh 150 ns cs-scl time cs t css 250 ns t csh 250 ns table 34 *1 the input signal rise and fall time ( t r , t f ) are specified at 15 ns or less. *2 all timing is specified using 20% and 80% of v dd as the standard.
sed1565 series 8C78 epson display control output timing figure 40 (v dd = 4.5 v to 5.5 v, ta = C40 to 85 c) item signal symbol condition rating units min typ max fr delay time fr t dfr c l = 50 pf 10 40 ns table 35 (v dd = 2.7 v to 4.5 v, ta = C40 to 85 c) item signal symbol condition rating units min typ max fr delay time fr t dfr c l = 50 pf 20 80 ns table 36 (v dd = 1.8 v to 2.7 v, ta = C40 to 85 c) item signal symbol condition rating units min typ max fr delay time fr t dfr c l = 50 pf 50 200 ns table 37 *1 valid only when the master mode is selected. *2 all timing is based on 20% and 80% of v dd . t dfr cl (out) fr
sed1565 series epson 8C79 sed1565 series (v dd = 4.5 v to 5.5 v, ta = C40 to 85 c) item signal symbol condition rating units min typ max reset time t r 0.5 m s reset l pulse width res t rw 0.5 m s table 38 (v dd = 2.7 v to 4.5 v, ta = C40 to 85 c) item signal symbol condition rating units min typ max reset time t r 1 m s reset l pulse width res t rw 1 m s table 39 (v dd = 1.8 v to 2.7 v, ta = C40 to 85 c) item signal symbol condition rating units min typ max reset time t r 1.5 m s reset l pulse width res t rw 1.5 m s *1 all timing is specified with 20% and 80% of v dd as the standard. table 40 reset timing figure 41 t rw t r reset complete during reset res internal status
sed1565 series 8C80 epson the mpu interface (reference examples) the sed1565 series can be connected to either 80 86 series mpus or to 68000 series mpus. moreover, using the serial interface it is possible to operate the sed1565 series chips with fewer signal lines. the display area can be enlarged by using multiple sed1565 series chips. when this is done, the chip select signal can be used to select the individual ics to access. (1) 8080 series mpus figure 42-1 (2) 6800 series mpus figure 42-2 (3) using the serial interface figure 42-3 v dd v cc gnd decoder reset mpu a0 d0 to d7 rd wr res cs1 cs2 a0 d0 to d7 rd wr res a1 to a7 iorq v dd c86 p/s v ss v ss sed1565 series v dd v cc gnd decoder reset mpu a0 d0 to d7 e r/w res cs1 cs2 a0 d0 to d7 e r/w res a1 to a15 vma v dd c86 p/s v ss v ss sed1565 series v dd v cc gnd decoder reset mpu a0 si scl res cs1 cs2 a0 port 1 port 2 res a1 to a7 v dd or v ss c86 p/s v ss v ss sed1565 series
sed1565 series epson 8C81 sed1565 series connections between lcd drivers (reference example) the liquid crystal display area can be enlarged with ease through the use of multiple sed1565 series chips. use a same equipment type. (1) sed1565 (master) ? sed1565 (slave) figure 43 v ss v dd m/s output input sed1565 series master m/s fr cl dof fr cl dof sed1565 series slave
sed1565 series 8C82 epson connections between lcd drivers (reference examples) the liquid crystal display area can be enlarged with ease through the use of multiple sed1565 series chips. use a same equipment type, in the composition of these chips. (1) single-chip structure figure 44-1 (2) double-chip structure, #1 figure 44-2 132 x 65 dots com seg com sed1565 series master 264 x 65 dots com com seg seg sed1565 series master sed1565 series slave
sed1565 series epson 8C83 sed1565 series fr cl dof cs1 cs2 res a0 wr,r/w rd, e d0 d1 d2 d3 d4 d5 d6, scl d7, si v dd v ss v ss2 v out cap3- cap1+ cap1- cap2- cap2+ vrs v dd v 1 v 2 v 3 v 4 v 5 vr v dd m/s cls c86 p/s hpm irs fr frs com s com 63 com 33 com 32 seg 131 seg 130 seg 1 seg 0 com s com 0 com 30 com 31 chip top view an example a sample tcp pin assignment sed1565t 0b tcp pin layout note: the following does not specify dimensions of the tcp pins.
sed1565 series 8C84 epson external view of tcp pins specifications ?base: u-rexs, 75 m ?copper foil: electrolytic copper foil, 25 m ?sn plating ?product pitch: 41p (19.0mm) ?solder resist positional tolerance: 0.3 (mold, marking area) (mold, marking area) (mold, marking area) (mold, marking area) section a section a section a output terminal pattern shape section b test pat detailed view
sed1565 series epson 8C85 sed1565 series notice please be advised on the following points in the use of this development manual. 1. this manual is subject to change without previous notice. 2. this manual does not guarantee or furnish the industrial property right nor its execution. application examples in the manual are intended to ensure your better understanding of the product. thus, the manufacturer shall not be liable for any trouble arising in your circuits from using such application example. numerical values provided in the property table of this manual are represented with their magnitude on the numerical line. 3. no part of this manual may not be reproduced, copied or used for commercial purposes without a written permission from the manufacturer. in handling of semiconductor devices, your attention is required to the following points. [precautions on light] property of semiconductor devices may be affected when they are exposed to light, possibly resulting in malfunctioning of the ics. to prevent such malfunctioning of the ics mounted on the boards or products, make sure that: (1) your design and mounting layout done are so that the ic is not exposed to light in actual use. (2) the ic is protected from light in the inspection process. (3) the ic is protected from light in its front, rear and side faces.

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